llvm-6502/test/CodeGen/Hexagon/tfr-to-combine.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

36 lines
741 B
LLVM

; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
; Check that we combine TFRs and TFRIs into COMBINEs.
@a = external global i16
@b = external global i16
@c = external global i16
; Function Attrs: nounwind
define i64 @test1() #0 {
; CHECK: combine(#10, #0)
entry:
store i16 0, i16* @a, align 2
store i16 10, i16* @b, align 2
ret i64 10
}
; Function Attrs: nounwind
define i64 @test2() #0 {
; CHECK: combine(#0, r{{[0-9]+}})
entry:
store i16 0, i16* @a, align 2
%0 = load i16, i16* @c, align 2
%conv2 = zext i16 %0 to i64
ret i64 %conv2
}
; Function Attrs: nounwind
define i64 @test4() #0 {
; CHECK: combine(#0, ##100)
entry:
store i16 100, i16* @b, align 2
store i16 0, i16* @a, align 2
ret i64 0
}