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0c5f5f4916
This way of using getNextOperandForReg() was unlikely to work as intended. We don't give any guarantees about the order of operands in the use-def chains, so looking only at operands following a given operand in the chain doesn't make sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161542 91177308-0d34-0410-b5e6-96231b3b80d8
648 lines
23 KiB
C++
648 lines
23 KiB
C++
//===-- HexagonHardwareLoops.cpp - Identify and generate hardware loops ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass identifies loops where we can generate the Hexagon hardware
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// loop instruction. The hardware loop can perform loop branches with a
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// zero-cycle overhead.
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//
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// The pattern that defines the induction variable can changed depending on
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// prior optimizations. For example, the IndVarSimplify phase run by 'opt'
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// normalizes induction variables, and the Loop Strength Reduction pass
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// run by 'llc' may also make changes to the induction variable.
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// The pattern detected by this phase is due to running Strength Reduction.
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//
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// Criteria for hardware loops:
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// - Countable loops (w/ ind. var for a trip count)
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// - Assumes loops are normalized by IndVarSimplify
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// - Try inner-most loops first
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// - No nested hardware loops.
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// - No function calls in loops.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "hwloops"
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#include "Hexagon.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/PassSupport.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include <algorithm>
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using namespace llvm;
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STATISTIC(NumHWLoops, "Number of loops converted to hardware loops");
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namespace {
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class CountValue;
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struct HexagonHardwareLoops : public MachineFunctionPass {
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MachineLoopInfo *MLI;
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MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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public:
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static char ID; // Pass identification, replacement for typeid
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HexagonHardwareLoops() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const { return "Hexagon Hardware Loops"; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// getCanonicalInductionVariable - Check to see if the loop has a canonical
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/// induction variable.
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/// Should be defined in MachineLoop. Based upon version in class Loop.
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const MachineInstr *getCanonicalInductionVariable(MachineLoop *L) const;
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/// getTripCount - Return a loop-invariant LLVM register indicating the
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/// number of times the loop will be executed. If the trip-count cannot
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/// be determined, this return null.
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CountValue *getTripCount(MachineLoop *L) const;
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/// isInductionOperation - Return true if the instruction matches the
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/// pattern for an opertion that defines an induction variable.
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bool isInductionOperation(const MachineInstr *MI, unsigned IVReg) const;
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/// isInvalidOperation - Return true if the instruction is not valid within
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/// a hardware loop.
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bool isInvalidLoopOperation(const MachineInstr *MI) const;
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/// containsInavlidInstruction - Return true if the loop contains an
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/// instruction that inhibits using the hardware loop.
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bool containsInvalidInstruction(MachineLoop *L) const;
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/// converToHardwareLoop - Given a loop, check if we can convert it to a
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/// hardware loop. If so, then perform the conversion and return true.
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bool convertToHardwareLoop(MachineLoop *L);
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};
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char HexagonHardwareLoops::ID = 0;
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// CountValue class - Abstraction for a trip count of a loop. A
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// smaller vesrsion of the MachineOperand class without the concerns
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// of changing the operand representation.
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class CountValue {
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public:
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enum CountValueType {
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CV_Register,
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CV_Immediate
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};
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private:
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CountValueType Kind;
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union Values {
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unsigned RegNum;
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int64_t ImmVal;
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Values(unsigned r) : RegNum(r) {}
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Values(int64_t i) : ImmVal(i) {}
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} Contents;
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bool isNegative;
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public:
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CountValue(unsigned r, bool neg) : Kind(CV_Register), Contents(r),
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isNegative(neg) {}
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explicit CountValue(int64_t i) : Kind(CV_Immediate), Contents(i),
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isNegative(i < 0) {}
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CountValueType getType() const { return Kind; }
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bool isReg() const { return Kind == CV_Register; }
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bool isImm() const { return Kind == CV_Immediate; }
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bool isNeg() const { return isNegative; }
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unsigned getReg() const {
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assert(isReg() && "Wrong CountValue accessor");
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return Contents.RegNum;
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}
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void setReg(unsigned Val) {
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Contents.RegNum = Val;
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}
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int64_t getImm() const {
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assert(isImm() && "Wrong CountValue accessor");
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if (isNegative) {
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return -Contents.ImmVal;
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}
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return Contents.ImmVal;
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}
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void setImm(int64_t Val) {
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Contents.ImmVal = Val;
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}
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void print(raw_ostream &OS, const TargetMachine *TM = 0) const {
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if (isReg()) { OS << PrintReg(getReg()); }
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if (isImm()) { OS << getImm(); }
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}
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};
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struct HexagonFixupHwLoops : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid.
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HexagonFixupHwLoops() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const { return "Hexagon Hardware Loop Fixup"; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// Maximum distance between the loop instr and the basic block.
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/// Just an estimate.
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static const unsigned MAX_LOOP_DISTANCE = 200;
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/// fixupLoopInstrs - Check the offset between each loop instruction and
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/// the loop basic block to determine if we can use the LOOP instruction
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/// or if we need to set the LC/SA registers explicitly.
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bool fixupLoopInstrs(MachineFunction &MF);
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/// convertLoopInstr - Add the instruction to set the LC and SA registers
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/// explicitly.
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void convertLoopInstr(MachineFunction &MF,
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MachineBasicBlock::iterator &MII,
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RegScavenger &RS);
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};
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char HexagonFixupHwLoops::ID = 0;
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} // end anonymous namespace
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/// isHardwareLoop - Returns true if the instruction is a hardware loop
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/// instruction.
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static bool isHardwareLoop(const MachineInstr *MI) {
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return MI->getOpcode() == Hexagon::LOOP0_r ||
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MI->getOpcode() == Hexagon::LOOP0_i;
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}
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/// isCompareEquals - Returns true if the instruction is a compare equals
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/// instruction with an immediate operand.
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static bool isCompareEqualsImm(const MachineInstr *MI) {
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return MI->getOpcode() == Hexagon::CMPEQri;
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}
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/// createHexagonHardwareLoops - Factory for creating
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/// the hardware loop phase.
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FunctionPass *llvm::createHexagonHardwareLoops() {
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return new HexagonHardwareLoops();
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}
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bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
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bool Changed = false;
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// get the loop information
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MLI = &getAnalysis<MachineLoopInfo>();
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// get the register information
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MRI = &MF.getRegInfo();
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// the target specific instructio info.
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TII = MF.getTarget().getInstrInfo();
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for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end();
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I != E; ++I) {
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MachineLoop *L = *I;
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if (!L->getParentLoop()) {
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Changed |= convertToHardwareLoop(L);
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}
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}
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return Changed;
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}
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/// getCanonicalInductionVariable - Check to see if the loop has a canonical
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/// induction variable. We check for a simple recurrence pattern - an
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/// integer recurrence that decrements by one each time through the loop and
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/// ends at zero. If so, return the phi node that corresponds to it.
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///
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/// Based upon the similar code in LoopInfo except this code is specific to
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/// the machine.
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/// This method assumes that the IndVarSimplify pass has been run by 'opt'.
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///
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const MachineInstr
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*HexagonHardwareLoops::getCanonicalInductionVariable(MachineLoop *L) const {
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MachineBasicBlock *TopMBB = L->getTopBlock();
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MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();
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assert(PI != TopMBB->pred_end() &&
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"Loop must have more than one incoming edge!");
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MachineBasicBlock *Backedge = *PI++;
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if (PI == TopMBB->pred_end()) return 0; // dead loop
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MachineBasicBlock *Incoming = *PI++;
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if (PI != TopMBB->pred_end()) return 0; // multiple backedges?
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// make sure there is one incoming and one backedge and determine which
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// is which.
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if (L->contains(Incoming)) {
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if (L->contains(Backedge))
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return 0;
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std::swap(Incoming, Backedge);
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} else if (!L->contains(Backedge))
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return 0;
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// Loop over all of the PHI nodes, looking for a canonical induction variable:
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// - The PHI node is "reg1 = PHI reg2, BB1, reg3, BB2".
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// - The recurrence comes from the backedge.
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// - the definition is an induction operatio.n
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for (MachineBasicBlock::iterator I = TopMBB->begin(), E = TopMBB->end();
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I != E && I->isPHI(); ++I) {
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const MachineInstr *MPhi = &*I;
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unsigned DefReg = MPhi->getOperand(0).getReg();
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for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
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// Check each operand for the value from the backedge.
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MachineBasicBlock *MBB = MPhi->getOperand(i+1).getMBB();
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if (L->contains(MBB)) { // operands comes from the backedge
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// Check if the definition is an induction operation.
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const MachineInstr *DI = MRI->getVRegDef(MPhi->getOperand(i).getReg());
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if (isInductionOperation(DI, DefReg)) {
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return MPhi;
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}
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}
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}
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}
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return 0;
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}
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/// getTripCount - Return a loop-invariant LLVM value indicating the
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/// number of times the loop will be executed. The trip count can
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/// be either a register or a constant value. If the trip-count
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/// cannot be determined, this returns null.
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///
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/// We find the trip count from the phi instruction that defines the
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/// induction variable. We follow the links to the CMP instruction
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/// to get the trip count.
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///
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/// Based upon getTripCount in LoopInfo.
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///
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CountValue *HexagonHardwareLoops::getTripCount(MachineLoop *L) const {
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// Check that the loop has a induction variable.
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const MachineInstr *IV_Inst = getCanonicalInductionVariable(L);
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if (IV_Inst == 0) return 0;
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// Canonical loops will end with a 'cmpeq_ri IV, Imm',
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// if Imm is 0, get the count from the PHI opnd
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// if Imm is -M, than M is the count
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// Otherwise, Imm is the count
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const MachineOperand *IV_Opnd;
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const MachineOperand *InitialValue;
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if (!L->contains(IV_Inst->getOperand(2).getMBB())) {
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InitialValue = &IV_Inst->getOperand(1);
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IV_Opnd = &IV_Inst->getOperand(3);
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} else {
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InitialValue = &IV_Inst->getOperand(3);
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IV_Opnd = &IV_Inst->getOperand(1);
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}
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// Look for the cmp instruction to determine if we
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// can get a useful trip count. The trip count can
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// be either a register or an immediate. The location
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// of the value depends upon the type (reg or imm).
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for (MachineRegisterInfo::reg_iterator
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RI = MRI->reg_begin(IV_Opnd->getReg()), RE = MRI->reg_end();
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RI != RE; ++RI) {
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IV_Opnd = &RI.getOperand();
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const MachineInstr *MI = IV_Opnd->getParent();
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if (L->contains(MI) && isCompareEqualsImm(MI)) {
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const MachineOperand &MO = MI->getOperand(2);
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assert(MO.isImm() && "IV Cmp Operand should be 0");
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int64_t ImmVal = MO.getImm();
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const MachineInstr *IV_DefInstr = MRI->getVRegDef(IV_Opnd->getReg());
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assert(L->contains(IV_DefInstr->getParent()) &&
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"IV definition should occurs in loop");
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int64_t iv_value = IV_DefInstr->getOperand(2).getImm();
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if (ImmVal == 0) {
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// Make sure the induction variable changes by one on each iteration.
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if (iv_value != 1 && iv_value != -1) {
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return 0;
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}
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return new CountValue(InitialValue->getReg(), iv_value > 0);
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} else {
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assert(InitialValue->isReg() && "Expecting register for init value");
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const MachineInstr *DefInstr = MRI->getVRegDef(InitialValue->getReg());
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if (DefInstr && DefInstr->getOpcode() == Hexagon::TFRI) {
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int64_t count = ImmVal - DefInstr->getOperand(1).getImm();
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if ((count % iv_value) != 0) {
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return 0;
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}
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return new CountValue(count/iv_value);
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}
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}
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}
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}
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return 0;
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}
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/// isInductionOperation - return true if the operation is matches the
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/// pattern that defines an induction variable:
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/// add iv, c
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///
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bool
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HexagonHardwareLoops::isInductionOperation(const MachineInstr *MI,
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unsigned IVReg) const {
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return (MI->getOpcode() ==
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Hexagon::ADD_ri && MI->getOperand(1).getReg() == IVReg);
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}
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/// isInvalidOperation - Return true if the operation is invalid within
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/// hardware loop.
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bool
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HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI) const {
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// call is not allowed because the callee may use a hardware loop
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if (MI->getDesc().isCall()) {
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return true;
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}
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// do not allow nested hardware loops
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if (isHardwareLoop(MI)) {
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return true;
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}
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// check if the instruction defines a hardware loop register
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef() &&
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(MO.getReg() == Hexagon::LC0 || MO.getReg() == Hexagon::LC1 ||
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MO.getReg() == Hexagon::SA0 || MO.getReg() == Hexagon::SA0)) {
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return true;
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}
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}
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return false;
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}
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/// containsInvalidInstruction - Return true if the loop contains
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/// an instruction that inhibits the use of the hardware loop function.
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///
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bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L) const {
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const std::vector<MachineBasicBlock*> Blocks = L->getBlocks();
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for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
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MachineBasicBlock *MBB = Blocks[i];
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for (MachineBasicBlock::iterator
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MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) {
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const MachineInstr *MI = &*MII;
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if (isInvalidLoopOperation(MI)) {
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return true;
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}
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}
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}
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return false;
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}
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/// converToHardwareLoop - check if the loop is a candidate for
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/// converting to a hardware loop. If so, then perform the
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/// transformation.
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///
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/// This function works on innermost loops first. A loop can
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/// be converted if it is a counting loop; either a register
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/// value or an immediate.
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///
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/// The code makes several assumptions about the representation
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/// of the loop in llvm.
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bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) {
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bool Changed = false;
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// Process nested loops first.
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for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
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Changed |= convertToHardwareLoop(*I);
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}
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// If a nested loop has been converted, then we can't convert this loop.
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if (Changed) {
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return Changed;
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}
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// Are we able to determine the trip count for the loop?
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CountValue *TripCount = getTripCount(L);
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if (TripCount == 0) {
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return false;
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}
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// Does the loop contain any invalid instructions?
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if (containsInvalidInstruction(L)) {
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return false;
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}
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MachineBasicBlock *Preheader = L->getLoopPreheader();
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// No preheader means there's not place for the loop instr.
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if (Preheader == 0) {
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return false;
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}
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MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();
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MachineBasicBlock *LastMBB = L->getExitingBlock();
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// Don't generate hw loop if the loop has more than one exit.
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if (LastMBB == 0) {
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return false;
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}
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MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
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// Determine the loop start.
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MachineBasicBlock *LoopStart = L->getTopBlock();
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if (L->getLoopLatch() != LastMBB) {
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// When the exit and latch are not the same, use the latch block as the
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// start.
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// The loop start address is used only after the 1st iteration, and the loop
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// latch may contains instrs. that need to be executed after the 1st iter.
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LoopStart = L->getLoopLatch();
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// Make sure the latch is a successor of the exit, otherwise it won't work.
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if (!LastMBB->isSuccessor(LoopStart)) {
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return false;
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}
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}
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// Convert the loop to a hardware loop
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DEBUG(dbgs() << "Change to hardware loop at "; L->dump());
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if (TripCount->isReg()) {
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// Create a copy of the loop count register.
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MachineFunction *MF = LastMBB->getParent();
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const TargetRegisterClass *RC =
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MF->getRegInfo().getRegClass(TripCount->getReg());
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unsigned CountReg = MF->getRegInfo().createVirtualRegister(RC);
|
|
BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY), CountReg).addReg(TripCount->getReg());
|
|
if (TripCount->isNeg()) {
|
|
unsigned CountReg1 = CountReg;
|
|
CountReg = MF->getRegInfo().createVirtualRegister(RC);
|
|
BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
|
|
TII->get(Hexagon::NEG), CountReg).addReg(CountReg1);
|
|
}
|
|
|
|
// Add the Loop instruction to the beginning of the loop.
|
|
BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
|
|
TII->get(Hexagon::LOOP0_r)).addMBB(LoopStart).addReg(CountReg);
|
|
} else {
|
|
assert(TripCount->isImm() && "Expecting immedate vaule for trip count");
|
|
// Add the Loop immediate instruction to the beginning of the loop.
|
|
int64_t CountImm = TripCount->getImm();
|
|
BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
|
|
TII->get(Hexagon::LOOP0_i)).addMBB(LoopStart).addImm(CountImm);
|
|
}
|
|
|
|
// Make sure the loop start always has a reference in the CFG. We need to
|
|
// create a BlockAddress operand to get this mechanism to work both the
|
|
// MachineBasicBlock and BasicBlock objects need the flag set.
|
|
LoopStart->setHasAddressTaken();
|
|
// This line is needed to set the hasAddressTaken flag on the BasicBlock
|
|
// object
|
|
BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
|
|
|
|
// Replace the loop branch with an endloop instruction.
|
|
DebugLoc dl = LastI->getDebugLoc();
|
|
BuildMI(*LastMBB, LastI, dl, TII->get(Hexagon::ENDLOOP0)).addMBB(LoopStart);
|
|
|
|
// The loop ends with either:
|
|
// - a conditional branch followed by an unconditional branch, or
|
|
// - a conditional branch to the loop start.
|
|
if (LastI->getOpcode() == Hexagon::JMP_c ||
|
|
LastI->getOpcode() == Hexagon::JMP_cNot) {
|
|
// delete one and change/add an uncond. branch to out of the loop
|
|
MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();
|
|
LastI = LastMBB->erase(LastI);
|
|
if (!L->contains(BranchTarget)) {
|
|
if (LastI != LastMBB->end()) {
|
|
TII->RemoveBranch(*LastMBB);
|
|
}
|
|
SmallVector<MachineOperand, 0> Cond;
|
|
TII->InsertBranch(*LastMBB, BranchTarget, 0, Cond, dl);
|
|
}
|
|
} else {
|
|
// Conditional branch to loop start; just delete it.
|
|
LastMBB->erase(LastI);
|
|
}
|
|
delete TripCount;
|
|
|
|
++NumHWLoops;
|
|
return true;
|
|
}
|
|
|
|
/// createHexagonFixupHwLoops - Factory for creating the hardware loop
|
|
/// phase.
|
|
FunctionPass *llvm::createHexagonFixupHwLoops() {
|
|
return new HexagonFixupHwLoops();
|
|
}
|
|
|
|
bool HexagonFixupHwLoops::runOnMachineFunction(MachineFunction &MF) {
|
|
DEBUG(dbgs() << "****** Hexagon Hardware Loop Fixup ******\n");
|
|
|
|
bool Changed = fixupLoopInstrs(MF);
|
|
return Changed;
|
|
}
|
|
|
|
/// fixupLoopInsts - For Hexagon, if the loop label is to far from the
|
|
/// loop instruction then we need to set the LC0 and SA0 registers
|
|
/// explicitly instead of using LOOP(start,count). This function
|
|
/// checks the distance, and generates register assignments if needed.
|
|
///
|
|
/// This function makes two passes over the basic blocks. The first
|
|
/// pass computes the offset of the basic block from the start.
|
|
/// The second pass checks all the loop instructions.
|
|
bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) {
|
|
|
|
// Offset of the current instruction from the start.
|
|
unsigned InstOffset = 0;
|
|
// Map for each basic block to it's first instruction.
|
|
DenseMap<MachineBasicBlock*, unsigned> BlockToInstOffset;
|
|
|
|
// First pass - compute the offset of each basic block.
|
|
for (MachineFunction::iterator MBB = MF.begin(), MBBe = MF.end();
|
|
MBB != MBBe; ++MBB) {
|
|
BlockToInstOffset[MBB] = InstOffset;
|
|
InstOffset += (MBB->size() * 4);
|
|
}
|
|
|
|
// Second pass - check each loop instruction to see if it needs to
|
|
// be converted.
|
|
InstOffset = 0;
|
|
bool Changed = false;
|
|
RegScavenger RS;
|
|
|
|
// Loop over all the basic blocks.
|
|
for (MachineFunction::iterator MBB = MF.begin(), MBBe = MF.end();
|
|
MBB != MBBe; ++MBB) {
|
|
InstOffset = BlockToInstOffset[MBB];
|
|
RS.enterBasicBlock(MBB);
|
|
|
|
// Loop over all the instructions.
|
|
MachineBasicBlock::iterator MIE = MBB->end();
|
|
MachineBasicBlock::iterator MII = MBB->begin();
|
|
while (MII != MIE) {
|
|
if (isHardwareLoop(MII)) {
|
|
RS.forward(MII);
|
|
assert(MII->getOperand(0).isMBB() &&
|
|
"Expect a basic block as loop operand");
|
|
int diff = InstOffset - BlockToInstOffset[MII->getOperand(0).getMBB()];
|
|
diff = (diff > 0 ? diff : -diff);
|
|
if ((unsigned)diff > MAX_LOOP_DISTANCE) {
|
|
// Convert to explicity setting LC0 and SA0.
|
|
convertLoopInstr(MF, MII, RS);
|
|
MII = MBB->erase(MII);
|
|
Changed = true;
|
|
} else {
|
|
++MII;
|
|
}
|
|
} else {
|
|
++MII;
|
|
}
|
|
InstOffset += 4;
|
|
}
|
|
}
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
/// convertLoopInstr - convert a loop instruction to a sequence of instructions
|
|
/// that set the lc and sa register explicitly.
|
|
void HexagonFixupHwLoops::convertLoopInstr(MachineFunction &MF,
|
|
MachineBasicBlock::iterator &MII,
|
|
RegScavenger &RS) {
|
|
const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
|
|
MachineBasicBlock *MBB = MII->getParent();
|
|
DebugLoc DL = MII->getDebugLoc();
|
|
unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0);
|
|
|
|
// First, set the LC0 with the trip count.
|
|
if (MII->getOperand(1).isReg()) {
|
|
// Trip count is a register
|
|
BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
|
|
.addReg(MII->getOperand(1).getReg());
|
|
} else {
|
|
// Trip count is an immediate.
|
|
BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFRI), Scratch)
|
|
.addImm(MII->getOperand(1).getImm());
|
|
BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
|
|
.addReg(Scratch);
|
|
}
|
|
// Then, set the SA0 with the loop start address.
|
|
BuildMI(*MBB, MII, DL, TII->get(Hexagon::CONST32_Label), Scratch)
|
|
.addMBB(MII->getOperand(0).getMBB());
|
|
BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::SA0).addReg(Scratch);
|
|
}
|