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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27053 91177308-0d34-0410-b5e6-96231b3b80d8
361 lines
14 KiB
C++
361 lines
14 KiB
C++
//===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by James M. Laskey and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a simple two pass scheduler. The first pass attempts to push
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// backward any lengthy instructions and critical paths. The second pass packs
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// instructions into semi-optimal time slots.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands (which do
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/// not go into the machine instrs.)
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static unsigned CountResults(SDNode *Node) {
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unsigned N = Node->getNumValues();
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while (N && Node->getValueType(N - 1) == MVT::Flag)
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--N;
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if (N && Node->getValueType(N - 1) == MVT::Other)
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--N; // Skip over chain result.
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return N;
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}
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/// CountOperands The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then flag operands. Compute the
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/// number of actual operands that will go into the machine instr.
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static unsigned CountOperands(SDNode *Node) {
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unsigned N = Node->getNumOperands();
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while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
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--N;
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if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
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--N; // Ignore chain if it exists.
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return N;
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}
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static unsigned CreateVirtualRegisters(MachineInstr *MI,
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unsigned NumResults,
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SSARegMap *RegMap,
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const TargetInstrDescriptor &II) {
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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const TargetOperandInfo *OpInfo = II.OpInfo;
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unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
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MI->addRegOperand(ResultReg, MachineOperand::Def);
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for (unsigned i = 1; i != NumResults; ++i) {
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assert(OpInfo[i].RegClass && "Isn't a register operand!");
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MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass),
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MachineOperand::Def);
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}
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return ResultReg;
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}
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) {
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std::map<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
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assert(I != VRBaseMap.end() && "Node emitted out of order - late");
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return I->second + Op.ResNo;
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}
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/// AddOperand - Add the specified operand to the specified machine instr. II
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding. IIOpNum and II are used for
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/// assertions only.
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void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
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unsigned IIOpNum,
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const TargetInstrDescriptor *II,
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std::map<SDNode*, unsigned> &VRBaseMap) {
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if (Op.isTargetOpcode()) {
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// Note that this case is redundant with the final else block, but we
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// include it because it is the most common and it makes the logic
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// simpler here.
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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// Get/emit the operand.
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unsigned VReg = getVR(Op, VRBaseMap);
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MI->addRegOperand(VReg, MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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if (II) {
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assert(II->OpInfo[IIOpNum].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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}
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} else if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Op)) {
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MI->addZeroExtImm64Operand(C->getValue());
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} else if (RegisterSDNode*R =
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dyn_cast<RegisterSDNode>(Op)) {
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MI->addRegOperand(R->getReg(), MachineOperand::Use);
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} else if (GlobalAddressSDNode *TGA =
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dyn_cast<GlobalAddressSDNode>(Op)) {
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MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
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} else if (BasicBlockSDNode *BB =
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dyn_cast<BasicBlockSDNode>(Op)) {
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MI->addMachineBasicBlockOperand(BB->getBasicBlock());
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} else if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(Op)) {
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MI->addFrameIndexOperand(FI->getIndex());
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} else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(Op)) {
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int Offset = CP->getOffset();
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unsigned Align = CP->getAlignment();
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// MachineConstantPool wants an explicit alignment.
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if (Align == 0) {
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if (CP->get()->getType() == Type::DoubleTy)
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Align = 3; // always 8-byte align doubles.
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else {
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Align = TM.getTargetData()
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.getTypeAlignmentShift(CP->get()->getType());
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if (Align == 0) {
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// Alignment of packed types. FIXME!
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Align = TM.getTargetData().getTypeSize(CP->get()->getType());
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Align = Log2_64(Align);
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}
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}
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}
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unsigned Idx = ConstPool->getConstantPoolIndex(CP->get(), Align);
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MI->addConstantPoolIndexOperand(Idx, Offset);
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} else if (ExternalSymbolSDNode *ES =
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dyn_cast<ExternalSymbolSDNode>(Op)) {
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MI->addExternalSymbolOperand(ES->getSymbol(), false);
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} else {
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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unsigned VReg = getVR(Op, VRBaseMap);
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MI->addRegOperand(VReg, MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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if (II) {
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assert(II->OpInfo[IIOpNum].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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}
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}
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}
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/// EmitNode - Generate machine code for an node and needed dependencies.
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///
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void ScheduleDAG::EmitNode(SDNode *Node,
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std::map<SDNode*, unsigned> &VRBaseMap) {
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unsigned VRBase = 0; // First virtual register for node
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// If machine instruction
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if (Node->isTargetOpcode()) {
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unsigned Opc = Node->getTargetOpcode();
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const TargetInstrDescriptor &II = TII->get(Opc);
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unsigned NumResults = CountResults(Node);
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unsigned NodeOperands = CountOperands(Node);
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unsigned NumMIOperands = NodeOperands + NumResults;
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#ifndef NDEBUG
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assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
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"#operands for dag node doesn't match .td file!");
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#endif
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// Create the new machine instruction.
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MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
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// Add result register values for things that are defined by this
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// instruction.
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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if (NumResults == 1) {
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *Use = *UI;
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if (Use->getOpcode() == ISD::CopyToReg &&
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Use->getOperand(2).Val == Node) {
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unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(Reg)) {
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VRBase = Reg;
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MI->addRegOperand(Reg, MachineOperand::Def);
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break;
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}
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}
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}
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}
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// Otherwise, create new virtual registers.
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if (NumResults && VRBase == 0)
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VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, II);
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// Emit all of the actual operands of this instruction, adding them to the
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// instruction as appropriate.
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for (unsigned i = 0; i != NodeOperands; ++i)
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AddOperand(MI, Node->getOperand(i), i+NumResults, &II, VRBaseMap);
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// Now that we have emitted all operands, emit this instruction itself.
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if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
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BB->insert(BB->end(), MI);
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} else {
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// Insert this instruction into the end of the basic block, potentially
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// taking some custom action.
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BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
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}
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} else {
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switch (Node->getOpcode()) {
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default:
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Node->dump();
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assert(0 && "This target-independent node should have been selected!");
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case ISD::EntryToken: // fall thru
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case ISD::TokenFactor:
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break;
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case ISD::CopyToReg: {
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unsigned InReg = getVR(Node->getOperand(2), VRBaseMap);
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unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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if (InReg != DestReg) // Coalesced away the copy?
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MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
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RegMap->getRegClass(InReg));
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break;
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}
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case ISD::CopyFromReg: {
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unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(SrcReg)) {
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VRBase = SrcReg; // Just use the input register directly!
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break;
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}
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *Use = *UI;
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if (Use->getOpcode() == ISD::CopyToReg &&
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Use->getOperand(2).Val == Node) {
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unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(DestReg)) {
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VRBase = DestReg;
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break;
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}
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}
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}
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// Figure out the register class to create for the destreg.
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const TargetRegisterClass *TRC = 0;
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if (VRBase) {
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TRC = RegMap->getRegClass(VRBase);
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} else {
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// Pick the register class of the right type that contains this physreg.
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for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
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E = MRI->regclass_end(); I != E; ++I)
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if ((*I)->hasType(Node->getValueType(0)) &&
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(*I)->contains(SrcReg)) {
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TRC = *I;
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break;
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}
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assert(TRC && "Couldn't find register class for reg copy!");
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// Create the reg, emit the copy.
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VRBase = RegMap->createVirtualRegister(TRC);
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}
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MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
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break;
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}
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case ISD::INLINEASM: {
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unsigned NumOps = Node->getNumOperands();
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if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
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--NumOps; // Ignore the flag operand.
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// Create the inline asm machine instruction.
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MachineInstr *MI =
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new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
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// Add the asm string as an external symbol operand.
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const char *AsmStr =
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cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
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MI->addExternalSymbolOperand(AsmStr, false);
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// Add all of the operand registers to the instruction.
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for (unsigned i = 2; i != NumOps;) {
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unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
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unsigned NumVals = Flags >> 3;
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MI->addZeroExtImm64Operand(Flags);
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++i; // Skip the ID value.
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switch (Flags & 7) {
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default: assert(0 && "Bad flags!");
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case 1: // Use of register.
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for (; NumVals; --NumVals, ++i) {
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
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MI->addMachineRegOperand(Reg, MachineOperand::Use);
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}
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break;
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case 2: // Def of register.
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for (; NumVals; --NumVals, ++i) {
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
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MI->addMachineRegOperand(Reg, MachineOperand::Def);
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}
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break;
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case 3: { // Immediate.
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assert(NumVals == 1 && "Unknown immediate value!");
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uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
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MI->addZeroExtImm64Operand(Val);
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++i;
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break;
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}
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case 4: // Addressing mode.
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// The addressing mode has been selected, just add all of the
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// operands to the machine instruction.
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for (; NumVals; --NumVals, ++i)
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AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
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break;
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}
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}
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break;
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}
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}
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}
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assert(!VRBaseMap.count(Node) && "Node emitted out of order - early");
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VRBaseMap[Node] = VRBase;
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}
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void ScheduleDAG::EmitNoop() {
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TII->insertNoop(*BB, BB->end());
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}
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/// Run - perform scheduling.
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///
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MachineBasicBlock *ScheduleDAG::Run() {
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TII = TM.getInstrInfo();
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MRI = TM.getRegisterInfo();
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RegMap = BB->getParent()->getSSARegMap();
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ConstPool = BB->getParent()->getConstantPool();
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Schedule();
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return BB;
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}
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