llvm-6502/lib/CodeGen/SelectionDAG
Arnold Schwaighofer e737018a86 DAGCombiner: Merge store/loads when we have extload/truncstores
This is helps on architectures where i8,i16 are not legal but we have byte, and
short loads/stores. Allowing us to merge copies like the one below on ARM.

copy(char *a, char *b, int n) {
 do {
   int t0 = a[0];
   int t1 = a[1];
   b[0] = t0;
   b[1] = t1;

radar://13536387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02 15:58:51 +00:00
..
CMakeLists.txt
DAGCombiner.cpp DAGCombiner: Merge store/loads when we have extload/truncstores 2013-04-02 15:58:51 +00:00
FastISel.cpp
FunctionLoweringInfo.cpp
InstrEmitter.cpp
InstrEmitter.h
LegalizeDAG.cpp
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp
LegalizeVectorTypes.cpp
LLVMBuild.txt
Makefile
ResourcePriorityQueue.cpp
ScheduleDAGFast.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp
ScheduleDAGSDNodes.h
ScheduleDAGVLIW.cpp
SDNodeDbgValue.h
SDNodeOrdering.h
SelectionDAG.cpp
SelectionDAGBuilder.cpp
SelectionDAGBuilder.h
SelectionDAGDumper.cpp
SelectionDAGISel.cpp
SelectionDAGPrinter.cpp
TargetLowering.cpp
TargetSelectionDAGInfo.cpp