mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-18 13:34:04 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
143 lines
4.3 KiB
LLVM
143 lines
4.3 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vsras8:
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;CHECK: ssra.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
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%tmp4 = add <8 x i8> %tmp1, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vsras16:
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;CHECK: ssra.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
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%tmp4 = add <4 x i16> %tmp1, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vsras32:
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;CHECK: ssra.2s
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 >
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%tmp4 = add <2 x i32> %tmp1, %tmp3
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ret <2 x i32> %tmp4
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}
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define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vsraQs8:
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;CHECK: ssra.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
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%tmp4 = add <16 x i8> %tmp1, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vsraQs16:
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;CHECK: ssra.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
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%tmp4 = add <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vsraQs32:
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;CHECK: ssra.4s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
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%tmp4 = add <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: vsraQs64:
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;CHECK: ssra.2d
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 >
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%tmp4 = add <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vsrau8:
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;CHECK: usra.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
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%tmp4 = add <8 x i8> %tmp1, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vsrau16:
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;CHECK: usra.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
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%tmp4 = add <4 x i16> %tmp1, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vsrau32:
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;CHECK: usra.2s
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 >
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%tmp4 = add <2 x i32> %tmp1, %tmp3
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ret <2 x i32> %tmp4
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}
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define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vsraQu8:
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;CHECK: usra.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
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%tmp4 = add <16 x i8> %tmp1, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vsraQu16:
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;CHECK: usra.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
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%tmp4 = add <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vsraQu32:
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;CHECK: usra.4s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
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%tmp4 = add <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: vsraQu64:
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;CHECK: usra.2d
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 >
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%tmp4 = add <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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