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https://github.com/c64scene-ar/llvm-6502.git
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LLVM backend for 6502
442f620296
Add a pass AArch64InterleavedAccess to identify and match interleaved memory accesses. This pass transforms an interleaved load/store into ldN/stN intrinsic. As Loop Vectorizor disables optimization on interleaved accesses by default, this optimization is also disabled by default. To enable it by "-aarch64-interleaved-access-opt=true"
E.g. Transform an interleaved load (Factor = 2):
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
%v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
Into:
%ld2 = { <4 x i32>, <4 x i32> } call aarch64.neon.ld2(%ptr)
%v0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
%v1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
E.g. Transform an interleaved store (Factor = 2):
%i.vec = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7> ; Interleaved vec
store <8 x i32> %i.vec, <8 x i32>* %ptr
Into:
%v0 = shuffle %i.vec, undef, <0, 1, 2, 3>
%v1 = shuffle %i.vec, undef, <4, 5, 6, 7>
call void aarch64.neon.st2(%v0, %v1, %ptr)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239514 91177308-0d34-0410-b5e6-96231b3b80d8
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