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llvm-6502/lib/Target/R600
History
Tom Stellard 9a6e4f08fe R600/SI: Remove SIISelLowering::legalizeOperands() 
Its functionality has been replaced by calling
SIInstrInfo::legalizeOperands() from
SIISelLowering::AdjstInstrPostInstrSelection() and running the
SIFoldOperands and SIShrinkInstructions passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225445 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 15:08:17 +00:00
..
AsmParser R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
InstPrinter R600/SI: Fix f64 inline immediates 2014-12-17 21:04:08 +00:00
MCTargetDesc R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
TargetInfo R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPU.h R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPU.td R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPUAsmPrinter.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
AMDGPUAsmPrinter.h R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 2014-12-02 22:00:07 +00:00
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td R600/SI: Add class intrinsic 2015-01-06 23:00:37 +00:00
AMDGPUInstructions.td R600/SI: Make more unordered comparisons legal 2014-12-11 22:15:39 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
AMDGPUISelLowering.cpp [SelectionDAG] Allow targets to specify legality of extloads' result 2015-01-08 00:51:32 +00:00
AMDGPUISelLowering.h R600/SI: Add class intrinsic 2015-01-06 23:00:37 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp R600/SI: Fix f64 inline immediates 2014-12-17 21:04:08 +00:00
AMDGPUMCInstLower.h R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
AMDGPUPromoteAlloca.cpp
AMDGPURegisterInfo.cpp R600/SI: Enable inline assembly 2014-12-03 04:08:00 +00:00
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 2014-12-02 22:00:07 +00:00
AMDGPUSubtarget.h R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
AMDGPUTargetMachine.cpp R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPUTargetMachine.h R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPUTargetTransformInfo.cpp
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 2014-12-02 22:00:07 +00:00
CaymanInstructions.td
CIInstructions.td R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
CMakeLists.txt
EvergreenInstructions.td
LLVMBuild.txt
Makefile
Processors.td R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td R600/SI: Use unordered not equal instructions 2014-12-11 22:15:35 +00:00
R600Intrinsics.td
R600ISelLowering.cpp [SelectionDAG] Allow targets to specify legality of extloads' result 2015-01-08 00:51:32 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h R600/SI: Add class intrinsic 2015-01-06 23:00:37 +00:00
SIFixSGPRCopies.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIFixSGPRLiveRanges.cpp
SIFoldOperands.cpp R600/SI: Commute instructions to enable more folding opportunities 2015-01-07 22:44:19 +00:00
SIInsertWaits.cpp R600/SI: Insert s_waitcnt before s_barrier instructions. 2015-01-06 19:52:07 +00:00
SIInstrFormats.td R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
SIInstrInfo.cpp R600/SI: Commute instructions to enable more folding opportunities 2015-01-07 22:44:19 +00:00
SIInstrInfo.h R600/SI: Teach SIFoldOperands to split 64-bit constants when folding 2015-01-07 19:56:17 +00:00
SIInstrInfo.td R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIInstructions.td R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIIntrinsics.td
SIISelLowering.cpp R600/SI: Remove SIISelLowering::legalizeOperands() 2015-01-08 15:08:17 +00:00
SIISelLowering.h R600/SI: Remove SIISelLowering::legalizeOperands() 2015-01-08 15:08:17 +00:00
SILoadStoreOptimizer.cpp R600/SI: Fix live range error hidden by SIFoldOperands 2014-12-03 05:22:29 +00:00
SILowerControlFlow.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SILowerI1Copies.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIRegisterInfo.h R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIRegisterInfo.td R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SISchedule.td
SIShrinkInstructions.cpp R600/SI: Move continue after checking s_mov_b32. 2014-12-08 19:55:43 +00:00
SITypeRewriter.cpp
VIInstrFormats.td R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
VIInstructions.td R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00