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Before this change, the SystemZ backend would use BRCL for all branches and only consider shortening them to BRC when generating an object file. E.g. a branch on equal would use the JGE alias of BRCL in assembly output, but might be shortened to the JE alias of BRC in ELF output. This was a useful first step, but it had two problems: (1) The z assembler isn't traditionally supposed to perform branch shortening or branch relaxation. We followed this rule by not relaxing branches in assembler input, but that meant that generating assembly code and then assembling it would not produce the same result as going directly to object code; the former would give long branches everywhere, whereas the latter would use short branches where possible. (2) Other useful branches, like COMPARE AND BRANCH, do not have long forms. We would need to do something else before supporting them. (Although COMPARE AND BRANCH does not change the condition codes, the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction during codegen, so that we can safely lower it to a separate compare and long branch where necessary. This is not a valid transformation for the assembler proper to make.) This patch therefore moves branch relaxation to a pre-emit pass. For now, calls are still shortened from BRASL to BRAS by the assembler, although this too is not really the traditional behaviour. The first test takes about 1.5s to run, and there are likely to be more tests in this vein once further branch types are added. The feeling on IRC was that 1.5s is a bit much for a single test, so I've restricted it to SystemZ hosts for now. The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests. A later patch will remove the {{g}}s from that directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182274 91177308-0d34-0410-b5e6-96231b3b80d8
227 lines
5.9 KiB
Plaintext
227 lines
5.9 KiB
Plaintext
//===---------------------------------------------------------------------===//
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// Random notes about and ideas for the SystemZ backend.
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//===---------------------------------------------------------------------===//
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The initial backend is deliberately restricted to z10. We should add support
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for later architectures at some point.
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--
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SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand() is passed "m" for all
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inline asm memory constraints; it doesn't get to see the original constraint.
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This means that it must conservatively treat all inline asm constraints
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as the most restricted type, "R".
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--
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If an inline asm ties an i32 "r" result to an i64 input, the input
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will be treated as an i32, leaving the upper bits uninitialised.
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For example:
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define void @f4(i32 *%dst) {
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%val = call i32 asm "blah $0", "=r,0" (i64 103)
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store i32 %val, i32 *%dst
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ret void
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}
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from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
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to load 103. This seems to be a general target-independent problem.
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--
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The tuning of the choice between LOAD ADDRESS (LA) and addition in
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SystemZISelDAGToDAG.cpp is suspect. It should be tweaked based on
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performance measurements.
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--
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We don't support tail calls at present.
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--
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We don't support prefetching yet.
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--
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There is no scheduling support.
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--
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We don't use the BRANCH ON COUNT or BRANCH ON INDEX families of instruction.
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--
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We might want to use BRANCH ON CONDITION for conditional indirect calls
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and conditional returns.
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--
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We don't use the combined COMPARE AND BRANCH instructions.
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--
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We should probably model just CC, not the PSW as a whole. Strictly
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speaking, every instruction changes the PSW since the PSW contains the
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current instruction address.
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--
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We don't use the condition code results of anything except comparisons.
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Implementing this may need something more finely grained than the z_cmp
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and z_ucmp that we have now. It might (or might not) also be useful to
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have a mask of "don't care" values in conditional branches. For example,
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integer comparisons never set CC to 3, so the bottom bit of the CC mask
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isn't particularly relevant. JNLH and JE are equally good for testing
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equality after an integer comparison, etc.
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--
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We don't use the LOAD AND TEST or TEST DATA CLASS instructions.
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--
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We could use the generic floating-point forms of LOAD COMPLEMENT,
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LOAD NEGATIVE and LOAD POSITIVE in cases where we don't need the
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condition codes. For example, we could use LCDFR instead of LCDBR.
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--
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We don't optimize block memory operations.
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It's definitely worth using things like MVC, CLC, NC, XC and OC with
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constant lengths. MVCIN may be worthwhile too.
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We should probably implement things like memcpy using MVC with EXECUTE.
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Likewise memcmp and CLC. MVCLE and CLCLE could be useful too.
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--
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We don't optimize string operations.
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MVST, CLST, SRST and CUSE could be useful here. Some of the TRANSLATE
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family might be too, although they are probably more difficult to exploit.
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--
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We don't take full advantage of builtins like fabsl because the calling
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conventions require f128s to be returned by invisible reference.
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--
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ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to
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produce a carry. SUBTRACT LOGICAL IMMEDIATE could be useful when we
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need to produce a borrow. (Note that there are no memory forms of
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ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
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part of 128-bit memory operations would probably need to be done
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via a register.)
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--
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We don't use the halfword forms of LOAD REVERSED and STORE REVERSED
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(LRVH and STRVH).
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--
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We could take advantage of the various ... UNDER MASK instructions,
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such as ICM and STCM.
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--
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We could make more use of the ROTATE AND ... SELECTED BITS instructions.
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At the moment we only use RISBG, and only then for subword atomic operations.
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--
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DAGCombiner can detect integer absolute, but there's not yet an associated
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ISD opcode. We could add one and implement it using LOAD POSITIVE.
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Negated absolutes could use LOAD NEGATIVE.
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--
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DAGCombiner doesn't yet fold truncations of extended loads. Functions like:
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unsigned long f (unsigned long x, unsigned short *y)
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{
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return (x << 32) | *y;
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}
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therefore end up as:
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sllg %r2, %r2, 32
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llgh %r0, 0(%r3)
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lr %r2, %r0
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br %r14
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but truncating the load would give:
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sllg %r2, %r2, 32
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lh %r2, 0(%r3)
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br %r14
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--
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Functions like:
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define i64 @f1(i64 %a) {
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%and = and i64 %a, 1
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ret i64 %and
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}
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ought to be implemented as:
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lhi %r0, 1
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ngr %r2, %r0
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br %r14
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but two-address optimisations reverse the order of the AND and force:
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lhi %r0, 1
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ngr %r0, %r2
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lgr %r2, %r0
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br %r14
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CodeGen/SystemZ/and-04.ll has several examples of this.
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--
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Out-of-range displacements are usually handled by loading the full
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address into a register. In many cases it would be better to create
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an anchor point instead. E.g. for:
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define void @f4a(i128 *%aptr, i64 %base) {
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%addr = add i64 %base, 524288
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%bptr = inttoptr i64 %addr to i128 *
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%a = load volatile i128 *%aptr
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%b = load i128 *%bptr
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%add = add i128 %a, %b
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store i128 %add, i128 *%aptr
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ret void
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}
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(from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
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into separate registers, rather than using %base+524288 as a base for both.
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--
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Dynamic stack allocations round the size to 8 bytes and then allocate
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that rounded amount. It would be simpler to subtract the unrounded
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size from the copy of the stack pointer and then align the result.
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See CodeGen/SystemZ/alloca-01.ll for an example.
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--
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Atomic loads and stores use the default compare-and-swap based implementation.
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This is much too conservative in practice, since the architecture guarantees
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that 1-, 2-, 4- and 8-byte loads and stores to aligned addresses are
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inherently atomic.
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--
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If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.
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--
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We might want to model all access registers and use them to spill
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32-bit values.
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