mirror of
https://github.com/c64scene-ar/llvm-6502.git
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692ee102eb
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
2.4 KiB
TableGen
60 lines
2.4 KiB
TableGen
//===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the AMD Radeon GPUs.
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//
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//===----------------------------------------------------------------------===//
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// Inversion of CCIfInReg
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class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
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// Calling convention for SI
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def CC_SI : CallingConv<[
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CCIfInReg<CCIfType<[f32, i32] , CCAssignToReg<[
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SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
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SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15
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]>>>,
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CCIfInReg<CCIfType<[i64] , CCAssignToRegWithShadow<
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[ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14 ],
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[ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR12, SGPR15 ]
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>>>,
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CCIfNotInReg<CCIfType<[f32, i32] , CCAssignToReg<[
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VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31
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]>>>
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]>;
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// Calling convention for compute kernels
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def CC_AMDGPU_Kernel : CallingConv<[
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CCIfType<[v4i32, v4f32], CCAssignToStack <16, 16>>,
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CCIfType<[i64, f64, v2f32, v2i32], CCAssignToStack < 8, 8>>,
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CCIfType<[i32, f32], CCAssignToStack < 4, 4>>,
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CCIfType<[i16], CCAssignToStack < 2, 4>>,
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CCIfType<[i8], CCAssignToStack < 1, 4>>
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]>;
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def CC_AMDGPU : CallingConv<[
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CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>().getGeneration() == "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS && "
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"State.getMachineFunction().getInfo<SIMachineFunctionInfo>()->"#
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"ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_AMDGPU_Kernel>>,
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CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>().getGeneration() < "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS && "
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"State.getMachineFunction().getInfo<R600MachineFunctionInfo>()->"
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"ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_AMDGPU_Kernel>>,
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CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>()"#
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".getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS", CCDelegateTo<CC_SI>>
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]>;
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