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https://github.com/c64scene-ar/llvm-6502.git
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e1e0f485f9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93841 91177308-0d34-0410-b5e6-96231b3b80d8
225 lines
8.6 KiB
C++
225 lines
8.6 KiB
C++
//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCMCAsmInfo.h"
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#include "PPCTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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static const MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
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if (TheTriple.getOS() == Triple::Darwin)
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return new PPCMCAsmInfoDarwin(isPPC64);
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return new PPCLinuxMCAsmInfo(isPPC64);
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}
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extern "C" void LLVMInitializePowerPCTarget() {
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// Register the targets
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RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
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RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
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RegisterAsmInfoFn C(ThePPC32Target, createMCAsmInfo);
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RegisterAsmInfoFn D(ThePPC64Target, createMCAsmInfo);
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}
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PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
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const std::string &FS, bool is64Bit)
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: LLVMTargetMachine(T, TT),
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Subtarget(TT, FS, is64Bit),
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DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
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FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
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if (getRelocationModel() == Reloc::Default) {
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if (Subtarget.isDarwin())
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setRelocationModel(Reloc::DynamicNoPIC);
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else
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setRelocationModel(Reloc::Static);
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}
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}
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/// Override this for PowerPC. Tail merging happily breaks up instruction issue
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/// groups, which typically degrades performance.
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bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
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PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT,
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const std::string &FS)
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: PPCTargetMachine(T, TT, FS, false) {
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}
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PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT,
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const std::string &FS)
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: PPCTargetMachine(T, TT, FS, true) {
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Install an instruction selector.
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PM.add(createPPCISelDag(*this));
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return false;
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}
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bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Must run branch selection immediately preceding the asm printer.
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PM.add(createPPCBranchSelectionPass());
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return false;
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}
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bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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MachineCodeEmitter &MCE) {
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// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
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// FIXME: This should be moved to TargetJITInfo!!
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if (Subtarget.isPPC64()) {
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// We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
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// instructions to materialize arbitrary global variable + function +
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// constant pool addresses.
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setRelocationModel(Reloc::PIC_);
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// Temporary workaround for the inability of PPC64 JIT to handle jump
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// tables.
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DisableJumpTables = true;
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} else {
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setRelocationModel(Reloc::Static);
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}
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// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
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// writing?
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Subtarget.SetJITMode();
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCCodeEmitterPass(*this, MCE));
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return false;
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}
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bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE) {
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// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
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// FIXME: This should be moved to TargetJITInfo!!
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if (Subtarget.isPPC64()) {
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// We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
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// instructions to materialize arbitrary global variable + function +
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// constant pool addresses.
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setRelocationModel(Reloc::PIC_);
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// Temporary workaround for the inability of PPC64 JIT to handle jump
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// tables.
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DisableJumpTables = true;
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} else {
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setRelocationModel(Reloc::Static);
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}
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// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
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// writing?
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Subtarget.SetJITMode();
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCJITCodeEmitterPass(*this, JCE));
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return false;
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}
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bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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ObjectCodeEmitter &OCE) {
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// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
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// FIXME: This should be moved to TargetJITInfo!!
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if (Subtarget.isPPC64()) {
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// We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
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// instructions to materialize arbitrary global variable + function +
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// constant pool addresses.
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setRelocationModel(Reloc::PIC_);
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// Temporary workaround for the inability of PPC64 JIT to handle jump
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// tables.
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DisableJumpTables = true;
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} else {
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setRelocationModel(Reloc::Static);
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}
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// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
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// writing?
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Subtarget.SetJITMode();
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCObjectCodeEmitterPass(*this, OCE));
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return false;
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}
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bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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MachineCodeEmitter &MCE) {
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCCodeEmitterPass(*this, MCE));
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return false;
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}
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bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE) {
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCJITCodeEmitterPass(*this, JCE));
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return false;
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}
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bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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ObjectCodeEmitter &OCE) {
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCObjectCodeEmitterPass(*this, OCE));
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return false;
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}
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/// getLSDAEncoding - Returns the LSDA pointer encoding. The choices are 4-byte,
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/// 8-byte, and target default. The CIE is hard-coded to indicate that the LSDA
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/// pointer in the FDE section is an "sdata4", and should be encoded as a 4-byte
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/// pointer by default. However, some systems may require a different size due
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/// to bugs or other conditions. We will default to a 4-byte encoding unless the
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/// system tells us otherwise.
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///
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/// The issue is when the CIE says their is an LSDA. That mandates that every
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/// FDE have an LSDA slot. But if the function does not need an LSDA. There
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/// needs to be some way to signify there is none. The LSDA is encoded as
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/// pc-rel. But you don't look for some magic value after adding the pc. You
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/// have to look for a zero before adding the pc. The problem is that the size
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/// of the zero to look for depends on the encoding. The unwinder bug in SL is
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/// that it always checks for a pointer-size zero. So on x86_64 it looks for 8
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/// bytes of zero. If you have an LSDA, it works fine since the 8-bytes are
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/// non-zero so it goes ahead and then reads the value based on the encoding.
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/// But if you use sdata4 and there is no LSDA, then the test for zero gives a
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/// false negative and the unwinder thinks there is an LSDA.
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///
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/// FIXME: This call-back isn't good! We should be using the correct encoding
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/// regardless of the system. However, there are some systems which have bugs
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/// that prevent this from occuring.
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DwarfLSDAEncoding::Encoding PPCTargetMachine::getLSDAEncoding() const {
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if (Subtarget.isDarwin() && Subtarget.getDarwinVers() != 10)
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return DwarfLSDAEncoding::Default;
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return DwarfLSDAEncoding::EightByte;
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}
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