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https://github.com/c64scene-ar/llvm-6502.git
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320296a4cf
This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
3.0 KiB
C++
92 lines
3.0 KiB
C++
//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides ARM specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMMCTARGETDESC_H
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#define ARMMCTARGETDESC_H
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#include "llvm/Support/DataTypes.h"
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#include <string>
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namespace llvm {
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class formatted_raw_ostream;
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCInstPrinter;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCStreamer;
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class MCRelocationInfo;
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class StringRef;
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class Target;
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class raw_ostream;
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extern Target TheARMTarget, TheThumbTarget;
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namespace ARM_MC {
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std::string ParseARMTriple(StringRef TT, StringRef CPU);
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/// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
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/// This is exposed so Asm parser, etc. do not need to go through
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/// TargetRegistry.
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MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS);
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}
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MCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
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bool isVerboseAsm, bool useLoc, bool useCFI,
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bool useDwarfDirectory,
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MCInstPrinter *InstPrint, MCCodeEmitter *CE,
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MCAsmBackend *TAB, bool ShowInst);
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MCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx);
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MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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/// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
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MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
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uint8_t OSABI);
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/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
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MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
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bool Is64Bit,
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uint32_t CPUType,
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uint32_t CPUSubtype);
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/// createARMMachORelocationInfo - Construct ARM Mach-O relocation info.
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MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
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} // End llvm namespace
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// Defines symbolic names for ARM registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "ARMGenRegisterInfo.inc"
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// Defines symbolic names for the ARM instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "ARMGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "ARMGenSubtargetInfo.inc"
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#endif
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