mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-03 15:29:28 +00:00
15983b80a0
Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.9 KiB
LLVM
58 lines
1.9 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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define void @t() nounwind ssp {
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; CHECK: t:
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entry:
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br i1 undef, label %return, label %if.end.i
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if.end.i: ; preds = %entry
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%tmp7.i = load i32* undef, align 4
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br i1 undef, label %return, label %if.end
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if.end: ; preds = %if.end.i
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; CHECK: %if.end
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; CHECK: movl (%{{.*}}), [[REG:%[a-z]+]]
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; CHECK-NOT: movl [[REG]], [[REG]]
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; CHECK-NEXT: testl [[REG]], [[REG]]
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; CHECK-NEXT: xorl
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%tmp138 = select i1 undef, i32 0, i32 %tmp7.i
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%tmp867 = zext i32 %tmp138 to i64
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br label %while.cond
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while.cond: ; preds = %while.body, %if.end
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%tmp869 = sub i64 %tmp867, 0
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%scale2.0 = trunc i64 %tmp869 to i32
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%cmp149 = icmp eq i32 %scale2.0, 0
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br i1 %cmp149, label %while.end, label %land.rhs
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land.rhs: ; preds = %while.cond
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br i1 undef, label %while.body, label %while.end
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while.body: ; preds = %land.rhs
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br label %while.cond
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while.end: ; preds = %land.rhs, %while.cond
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br i1 undef, label %cond.false205, label %cond.true190
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cond.true190: ; preds = %while.end
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br i1 undef, label %cond.false242, label %cond.true225
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cond.false205: ; preds = %while.end
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unreachable
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cond.true225: ; preds = %cond.true190
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br i1 undef, label %cond.false280, label %cond.true271
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cond.false242: ; preds = %cond.true190
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unreachable
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cond.true271: ; preds = %cond.true225
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unreachable
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cond.false280: ; preds = %cond.true225
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unreachable
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return: ; preds = %if.end.i, %entry
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ret void
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}
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