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booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
169 lines
6.4 KiB
C++
169 lines
6.4 KiB
C++
//===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file exposes functions that may be used with BuildMI from the
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// MachineInstrBuilder.h file to handle X86'isms in a clean way.
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//
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// The BuildMem function may be used with the BuildMI function to add entire
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// memory references in a single, typed, function call. X86 memory references
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// can be very complex expressions (described in the README), so wrapping them
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// up behind an easier to use interface makes sense. Descriptions of the
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// functions are included below.
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//
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// For reference, the order of operands for memory references is:
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// (Operand), Base, Scale, Index, Displacement.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86INSTRBUILDER_H
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#define X86INSTRBUILDER_H
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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namespace llvm {
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/// X86AddressMode - This struct holds a generalized full x86 address mode.
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/// The base register can be a frame index, which will eventually be replaced
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/// with BP or SP and Disp being offsetted accordingly. The displacement may
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/// also include the offset of a global value.
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struct X86AddressMode {
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enum {
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RegBase,
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FrameIndexBase
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} BaseType;
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union {
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unsigned Reg;
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int FrameIndex;
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} Base;
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unsigned Scale;
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unsigned IndexReg;
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unsigned Disp;
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GlobalValue *GV;
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X86AddressMode() : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0) {
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Base.Reg = 0;
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}
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};
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/// addDirectMem - This function is used to add a direct memory reference to the
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/// current instruction -- that is, a dereference of an address in a register,
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/// with no scale, index or displacement. An example is: DWORD PTR [EAX].
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///
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inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB,
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unsigned Reg) {
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// Because memory references are always represented with four
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// values, this adds: Reg, [1, NoReg, 0] to the instruction.
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return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
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}
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inline const MachineInstrBuilder &addLeaOffset(const MachineInstrBuilder &MIB,
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int Offset) {
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return MIB.addImm(1).addReg(0).addImm(Offset);
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}
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inline const MachineInstrBuilder &addOffset(const MachineInstrBuilder &MIB,
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int Offset) {
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return addLeaOffset(MIB, Offset).addReg(0);
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}
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/// addRegOffset - This function is used to add a memory reference of the form
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/// [Reg + Offset], i.e., one with no scale or index, but with a
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/// displacement. An example is: DWORD PTR [EAX + 4].
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///
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inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
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unsigned Reg, bool isKill,
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int Offset) {
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return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
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}
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inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB,
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unsigned Reg, bool isKill,
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int Offset) {
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return addLeaOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
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}
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/// addRegReg - This function is used to add a memory reference of the form:
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/// [Reg + Reg].
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inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
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unsigned Reg1, bool isKill1,
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unsigned Reg2, bool isKill2) {
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return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
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.addReg(Reg2, getKillRegState(isKill2)).addImm(0);
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}
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inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB,
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const X86AddressMode &AM) {
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assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
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if (AM.BaseType == X86AddressMode::RegBase)
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MIB.addReg(AM.Base.Reg);
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else if (AM.BaseType == X86AddressMode::FrameIndexBase)
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MIB.addFrameIndex(AM.Base.FrameIndex);
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else
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assert (0);
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MIB.addImm(AM.Scale).addReg(AM.IndexReg);
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if (AM.GV)
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return MIB.addGlobalAddress(AM.GV, AM.Disp);
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else
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return MIB.addImm(AM.Disp);
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}
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inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
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const X86AddressMode &AM) {
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return addLeaAddress(MIB, AM).addReg(0);
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}
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/// addFrameReference - This function is used to add a reference to the base of
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/// an abstract object on the stack frame of the current function. This
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/// reference has base register as the FrameIndex offset until it is resolved.
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/// This allows a constant offset to be specified as well...
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///
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inline const MachineInstrBuilder &
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addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
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MachineInstr *MI = MIB;
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MachineFunction &MF = *MI->getParent()->getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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const TargetInstrDesc &TID = MI->getDesc();
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unsigned Flags = 0;
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if (TID.mayLoad())
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Flags |= MachineMemOperand::MOLoad;
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if (TID.mayStore())
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Flags |= MachineMemOperand::MOStore;
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MachineMemOperand MMO(PseudoSourceValue::getFixedStack(FI),
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Flags,
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MFI.getObjectOffset(FI) + Offset,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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return addOffset(MIB.addFrameIndex(FI), Offset)
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.addMemOperand(MMO);
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}
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/// addConstantPoolReference - This function is used to add a reference to the
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/// base of a constant value spilled to the per-function constant pool. The
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/// reference uses the abstract ConstantPoolIndex which is retained until
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/// either machine code emission or assembly output. In PIC mode on x86-32,
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/// the GlobalBaseReg parameter can be used to make this a
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/// GlobalBaseReg-relative reference.
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///
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inline const MachineInstrBuilder &
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addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
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unsigned GlobalBaseReg = 0) {
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//FIXME: factor this
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return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
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.addConstantPoolIndex(CPI).addReg(0);
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}
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} // End llvm namespace
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#endif
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