llvm-6502/test/CodeGen
Chandler Carruth 454c3997b4 [x86] Teach the 128-bit vector shuffle lowering routines to take
advantage of the existence of a reasonable blend instruction.

The 256-bit vector shuffle lowering has leveraged the general technique
of decomposed shuffles and blends for quite some time, but this never
made it back into the 128-bit code, and there are a large number of
patterns where this is substantially better. For example, this removes
almost all domain crossing in vector shuffles that involve some blend
and some permutation with SSE4.1 and later. See the massive reduction
in 'shufps' for integer test cases in this commit.

This isn't perfect yet for a few reasons:

1) The v8i16 shuffle lowering continues to plague me. We don't always
   form an unpack-based blend when that would be better. But the wins
   pretty drastically outstrip the losses here.
2) The v16i8 shuffle lowering is just a disaster here. I never went and
   implemented blend support here for some terrible reason. I'll do
   that next probably. I've not updated it for now.

More variations on this technique are coming as well -- we don't
shuffle-into-unpack or shuffle-into-palignr, both of which would also be
profitable.

Note that some test cases grow significantly in the number of
instructions, but I expect to actually be faster. We use
pshufd+pshufd+blendw instead of a single shufps, but the pshufd's are
very likely to pipeline well (two ports on most modern intel chips) and
the blend is a *very* fast instruction. The domain switch penalty will
essentially always be more than a blend instruction, which is the only
increase in tree height.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229350 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-16 01:52:02 +00:00
..
AArch64 [SDAG] Teach the SelectionDAG to canonicalize vector shuffles of splats 2015-02-15 12:18:12 +00:00
ARM
BPF
CPP
Generic
Hexagon
Inputs
Mips [mips][microMIPS] Delay slot filler: Replace the microMIPS JR with the JRC 2015-02-13 17:51:27 +00:00
MSP430
NVPTX
PowerPC
R600 R600/SI: Implement correct f64 fdiv 2015-02-14 04:30:08 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86 [x86] Teach the 128-bit vector shuffle lowering routines to take 2015-02-16 01:52:02 +00:00
XCore