mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7627d9c229
A multiply cannot unsigned wrap if there are bitwidth, or more, leading zero bits between the two operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224849 91177308-0d34-0410-b5e6-96231b3b80d8
282 lines
7.1 KiB
LLVM
282 lines
7.1 KiB
LLVM
; This test makes sure that mul instructions are properly eliminated.
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i32 @test1(i32 %A) {
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; CHECK-LABEL: @test1(
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%B = mul i32 %A, 1 ; <i32> [#uses=1]
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ret i32 %B
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; CHECK: ret i32 %A
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}
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define i32 @test2(i32 %A) {
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; CHECK-LABEL: @test2(
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; Should convert to an add instruction
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%B = mul i32 %A, 2 ; <i32> [#uses=1]
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ret i32 %B
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; CHECK: shl i32 %A, 1
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}
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define i32 @test3(i32 %A) {
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; CHECK-LABEL: @test3(
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; This should disappear entirely
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%B = mul i32 %A, 0 ; <i32> [#uses=1]
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ret i32 %B
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; CHECK: ret i32 0
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}
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define double @test4(double %A) {
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; CHECK-LABEL: @test4(
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; This is safe for FP
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%B = fmul double 1.000000e+00, %A ; <double> [#uses=1]
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ret double %B
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; CHECK: ret double %A
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}
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define i32 @test5(i32 %A) {
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; CHECK-LABEL: @test5(
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%B = mul i32 %A, 8 ; <i32> [#uses=1]
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ret i32 %B
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; CHECK: shl i32 %A, 3
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}
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define i8 @test6(i8 %A) {
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; CHECK-LABEL: @test6(
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%B = mul i8 %A, 8 ; <i8> [#uses=1]
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%C = mul i8 %B, 8 ; <i8> [#uses=1]
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ret i8 %C
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; CHECK: shl i8 %A, 6
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}
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define i32 @test7(i32 %i) {
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; CHECK-LABEL: @test7(
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%tmp = mul i32 %i, -1 ; <i32> [#uses=1]
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ret i32 %tmp
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; CHECK: sub i32 0, %i
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}
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define i64 @test8(i64 %i) {
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; CHECK-LABEL: @test8(
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%j = mul i64 %i, -1 ; <i64> [#uses=1]
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ret i64 %j
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; CHECK: sub i64 0, %i
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}
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define i32 @test9(i32 %i) {
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; CHECK-LABEL: @test9(
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%j = mul i32 %i, -1 ; <i32> [#uses=1]
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ret i32 %j
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; CHECK: sub i32 0, %i
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}
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define i32 @test10(i32 %a, i32 %b) {
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; CHECK-LABEL: @test10(
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%c = icmp slt i32 %a, 0 ; <i1> [#uses=1]
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%d = zext i1 %c to i32 ; <i32> [#uses=1]
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; e = b & (a >> 31)
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%e = mul i32 %d, %b ; <i32> [#uses=1]
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ret i32 %e
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; CHECK: [[TEST10:%.*]] = ashr i32 %a, 31
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; CHECK-NEXT: %e = and i32 [[TEST10]], %b
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; CHECK-NEXT: ret i32 %e
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}
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define i32 @test11(i32 %a, i32 %b) {
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; CHECK-LABEL: @test11(
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%c = icmp sle i32 %a, -1 ; <i1> [#uses=1]
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%d = zext i1 %c to i32 ; <i32> [#uses=1]
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; e = b & (a >> 31)
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%e = mul i32 %d, %b ; <i32> [#uses=1]
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ret i32 %e
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; CHECK: [[TEST11:%.*]] = ashr i32 %a, 31
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; CHECK-NEXT: %e = and i32 [[TEST11]], %b
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; CHECK-NEXT: ret i32 %e
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}
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define i32 @test12(i32 %a, i32 %b) {
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; CHECK-LABEL: @test12(
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%c = icmp ugt i32 %a, 2147483647 ; <i1> [#uses=1]
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%d = zext i1 %c to i32 ; <i32> [#uses=1]
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%e = mul i32 %d, %b ; <i32> [#uses=1]
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ret i32 %e
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; CHECK: [[TEST12:%.*]] = ashr i32 %a, 31
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; CHECK-NEXT: %e = and i32 [[TEST12]], %b
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; CHECK-NEXT: ret i32 %e
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}
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; PR2642
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define internal void @test13(<4 x float>*) {
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; CHECK-LABEL: @test13(
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load <4 x float>* %0, align 1
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fmul <4 x float> %2, < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >
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store <4 x float> %3, <4 x float>* %0, align 1
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ret void
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; CHECK-NEXT: ret void
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}
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define <16 x i8> @test14(<16 x i8> %a) {
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; CHECK-LABEL: @test14(
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%b = mul <16 x i8> %a, zeroinitializer
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ret <16 x i8> %b
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; CHECK-NEXT: ret <16 x i8> zeroinitializer
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}
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; rdar://7293527
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define i32 @test15(i32 %A, i32 %B) {
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; CHECK-LABEL: @test15(
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entry:
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%shl = shl i32 1, %B
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%m = mul i32 %shl, %A
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ret i32 %m
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; CHECK: shl i32 %A, %B
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}
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; X * Y (when Y is 0 or 1) --> x & (0-Y)
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define i32 @test16(i32 %b, i1 %c) {
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; CHECK-LABEL: @test16(
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%d = zext i1 %c to i32 ; <i32> [#uses=1]
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; e = b & (a >> 31)
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%e = mul i32 %d, %b ; <i32> [#uses=1]
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ret i32 %e
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; CHECK: [[TEST16:%.*]] = select i1 %c, i32 %b, i32 0
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; CHECK-NEXT: ret i32 [[TEST16]]
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}
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; X * Y (when Y is 0 or 1) --> x & (0-Y)
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define i32 @test17(i32 %a, i32 %b) {
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; CHECK-LABEL: @test17(
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%a.lobit = lshr i32 %a, 31
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%e = mul i32 %a.lobit, %b
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ret i32 %e
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; CHECK: [[TEST17:%.*]] = ashr i32 %a, 31
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; CHECK-NEXT: %e = and i32 [[TEST17]], %b
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; CHECK-NEXT: ret i32 %e
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}
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define i32 @test18(i32 %A, i32 %B) {
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; CHECK-LABEL: @test18(
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%C = and i32 %A, 1
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%D = and i32 %B, 1
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%E = mul i32 %C, %D
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%F = and i32 %E, 16
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ret i32 %F
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; CHECK-NEXT: ret i32 0
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}
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declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32)
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declare void @use(i1)
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define i32 @test19(i32 %A, i32 %B) {
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; CHECK-LABEL: @test19(
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%C = and i32 %A, 1
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%D = and i32 %B, 1
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; It would be nice if we also started proving that this doesn't overflow.
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%E = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %C, i32 %D)
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%F = extractvalue {i32, i1} %E, 0
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%G = extractvalue {i32, i1} %E, 1
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call void @use(i1 %G)
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%H = and i32 %F, 16
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ret i32 %H
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; CHECK: ret i32 0
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}
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define <2 x i64> @test20(<2 x i64> %A) {
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; CHECK-LABEL: @test20(
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%B = add <2 x i64> %A, <i64 12, i64 14>
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%C = mul <2 x i64> %B, <i64 3, i64 2>
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ret <2 x i64> %C
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; CHECK: mul <2 x i64> %A, <i64 3, i64 2>
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; CHECK: add <2 x i64> %{{.}}, <i64 36, i64 28>
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}
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define <2 x i1> @test21(<2 x i1> %A, <2 x i1> %B) {
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; CHECK-LABEL: @test21(
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%C = mul <2 x i1> %A, %B
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ret <2 x i1> %C
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; CHECK: %C = and <2 x i1> %A, %B
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}
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define i32 @test22(i32 %A) {
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; CHECK-LABEL: @test22(
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%B = mul nsw i32 %A, -1
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ret i32 %B
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; CHECK: sub nsw i32 0, %A
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}
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define i32 @test23(i32 %A) {
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; CHECK-LABEL: @test23(
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%B = shl nuw i32 %A, 1
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%C = mul nuw i32 %B, 3
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ret i32 %C
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; CHECK: mul nuw i32 %A, 6
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}
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define i32 @test24(i32 %A) {
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; CHECK-LABEL: @test24(
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%B = shl nsw i32 %A, 1
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%C = mul nsw i32 %B, 3
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ret i32 %C
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; CHECK: mul nsw i32 %A, 6
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}
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define i32 @test25(i32 %A, i32 %B) {
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; CHECK-LABEL: @test25(
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%C = sub nsw i32 0, %A
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%D = sub nsw i32 0, %B
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%E = mul nsw i32 %C, %D
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ret i32 %E
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; CHECK: mul nsw i32 %A, %B
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}
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define i32 @test26(i32 %A, i32 %B) {
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; CHECK-LABEL: @test26(
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%C = shl nsw i32 1, %B
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%D = mul nsw i32 %A, %C
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ret i32 %D
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; CHECK: shl nsw i32 %A, %B
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}
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define i32 @test27(i32 %A, i32 %B) {
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; CHECK-LABEL: @test27(
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%C = shl i32 1, %B
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%D = mul nuw i32 %A, %C
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ret i32 %D
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; CHECK: shl nuw i32 %A, %B
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}
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define i32 @test28(i32 %A) {
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; CHECK-LABEL: @test28(
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%B = shl i32 1, %A
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%C = mul nsw i32 %B, %B
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ret i32 %C
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; CHECK: %[[shl1:.*]] = shl i32 1, %A
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; CHECK-NEXT: %[[shl2:.*]] = shl i32 %[[shl1]], %A
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; CHECK-NEXT: ret i32 %[[shl2]]
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}
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define i64 @test29(i31 %A, i31 %B) {
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; CHECK-LABEL: @test29(
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%C = sext i31 %A to i64
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%D = sext i31 %B to i64
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%E = mul i64 %C, %D
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ret i64 %E
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; CHECK: %[[sext1:.*]] = sext i31 %A to i64
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; CHECK-NEXT: %[[sext2:.*]] = sext i31 %B to i64
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; CHECK-NEXT: %[[mul:.*]] = mul nsw i64 %[[sext1]], %[[sext2]]
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; CHECK-NEXT: ret i64 %[[mul]]
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}
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define i64 @test30(i32 %A, i32 %B) {
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; CHECK-LABEL: @test30(
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%C = zext i32 %A to i64
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%D = zext i32 %B to i64
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%E = mul i64 %C, %D
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ret i64 %E
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; CHECK: %[[zext1:.*]] = zext i32 %A to i64
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; CHECK-NEXT: %[[zext2:.*]] = zext i32 %B to i64
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; CHECK-NEXT: %[[mul:.*]] = mul nuw i64 %[[zext1]], %[[zext2]]
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; CHECK-NEXT: ret i64 %[[mul]]
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}
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