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https://github.com/c64scene-ar/llvm-6502.git
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40e455d992
SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207591 91177308-0d34-0410-b5e6-96231b3b80d8
108 lines
2.9 KiB
LLVM
108 lines
2.9 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: @global_copy_i1_to_i1
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; SI: BUFFER_LOAD_UBYTE
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; SI: V_AND_B32_e32 v{{[0-9]+}}, 1
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; SI: BUFFER_STORE_BYTE
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; SI: S_ENDPGM
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define void @global_copy_i1_to_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
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%load = load i1 addrspace(1)* %in
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store i1 %load, i1 addrspace(1)* %out, align 1
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ret void
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}
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; SI-LABEL: @global_sextload_i1_to_i32
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; XSI: BUFFER_LOAD_BYTE
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; SI: BUFFER_STORE_DWORD
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; SI: S_ENDPGM
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define void @global_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
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%load = load i1 addrspace(1)* %in
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%ext = sext i1 %load to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @global_zextload_i1_to_i32
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_STORE_DWORD
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; SI: S_ENDPGM
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define void @global_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
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%load = load i1 addrspace(1)* %in
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%ext = zext i1 %load to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @global_sextload_i1_to_i64
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; XSI: BUFFER_LOAD_BYTE
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; SI: BUFFER_STORE_DWORDX2
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; SI: S_ENDPGM
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define void @global_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
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%load = load i1 addrspace(1)* %in
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%ext = sext i1 %load to i64
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store i64 %ext, i64 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @global_zextload_i1_to_i64
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_STORE_DWORDX2
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; SI: S_ENDPGM
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define void @global_zextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
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%load = load i1 addrspace(1)* %in
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%ext = zext i1 %load to i64
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store i64 %ext, i64 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @i1_arg
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; SI: BUFFER_LOAD_UBYTE
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; SI: V_AND_B32_e32
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; SI: BUFFER_STORE_BYTE
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; SI: S_ENDPGM
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define void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind {
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store i1 %x, i1 addrspace(1)* %out, align 1
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ret void
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}
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; SI-LABEL: @i1_arg_zext_i32
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_STORE_DWORD
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; SI: S_ENDPGM
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define void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwind {
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%ext = zext i1 %x to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @i1_arg_zext_i64
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; SI: BUFFER_LOAD_UBYTE
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; SI: BUFFER_STORE_DWORDX2
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; SI: S_ENDPGM
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define void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwind {
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%ext = zext i1 %x to i64
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store i64 %ext, i64 addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: @i1_arg_sext_i32
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; XSI: BUFFER_LOAD_BYTE
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; SI: BUFFER_STORE_DWORD
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; SI: S_ENDPGM
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define void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwind {
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%ext = sext i1 %x to i32
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store i32 %ext, i32addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @i1_arg_sext_i64
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; XSI: BUFFER_LOAD_BYTE
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; SI: BUFFER_STORE_DWORDX2
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; SI: S_ENDPGM
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define void @i1_arg_sext_i64(i64 addrspace(1)* %out, i1 %x) nounwind {
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%ext = sext i1 %x to i64
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store i64 %ext, i64 addrspace(1)* %out, align 8
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ret void
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}
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