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https://github.com/c64scene-ar/llvm-6502.git
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40e455d992
SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207591 91177308-0d34-0410-b5e6-96231b3b80d8
159 lines
6.0 KiB
LLVM
159 lines
6.0 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: @local_i32_load
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; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x1c, [M0]
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; SI: BUFFER_STORE_DWORD [[REG]],
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define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
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%gep = getelementptr i32 addrspace(3)* %in, i32 7
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%val = load i32 addrspace(3)* %gep, align 4
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @local_i32_load_0_offset
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; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x0, [M0]
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; SI: BUFFER_STORE_DWORD [[REG]],
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define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
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%val = load i32 addrspace(3)* %in, align 4
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @local_i8_load_i16_max_offset
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; SI-NOT: ADD
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; SI: DS_READ_U8 [[REG:v[0-9]+]], {{v[0-9]+}}, 0xffff, [M0]
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; SI: BUFFER_STORE_BYTE [[REG]],
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define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
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%gep = getelementptr i8 addrspace(3)* %in, i32 65535
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%val = load i8 addrspace(3)* %gep, align 4
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store i8 %val, i8 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @local_i8_load_over_i16_max_offset
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; SI: S_ADD_I32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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; SI: V_MOV_B32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
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; SI: DS_READ_U8 [[REG:v[0-9]+]], [[VREGADDR]], 0x0, [M0]
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; SI: BUFFER_STORE_BYTE [[REG]],
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define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
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%gep = getelementptr i8 addrspace(3)* %in, i32 65536
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%val = load i8 addrspace(3)* %gep, align 4
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store i8 %val, i8 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @local_i64_load
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; SI-NOT: ADD
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; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
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; SI: BUFFER_STORE_DWORDX2 [[REG]],
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define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
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%gep = getelementptr i64 addrspace(3)* %in, i32 7
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%val = load i64 addrspace(3)* %gep, align 8
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store i64 %val, i64 addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: @local_i64_load_0_offset
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; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
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; SI: BUFFER_STORE_DWORDX2 [[REG]],
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define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
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%val = load i64 addrspace(3)* %in, align 8
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store i64 %val, i64 addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: @local_f64_load
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; SI-NOT: ADD
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; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
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; SI: BUFFER_STORE_DWORDX2 [[REG]],
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define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
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%gep = getelementptr double addrspace(3)* %in, i32 7
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%val = load double addrspace(3)* %gep, align 8
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store double %val, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: @local_f64_load_0_offset
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; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
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; SI: BUFFER_STORE_DWORDX2 [[REG]],
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define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
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%val = load double addrspace(3)* %in, align 8
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store double %val, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: @local_i64_store
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; SI-NOT: ADD
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; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
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define void @local_i64_store(i64 addrspace(3)* %out) nounwind {
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%gep = getelementptr i64 addrspace(3)* %out, i32 7
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store i64 5678, i64 addrspace(3)* %gep, align 8
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ret void
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}
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; SI-LABEL: @local_i64_store_0_offset
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; SI-NOT: ADD
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; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
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define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
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store i64 1234, i64 addrspace(3)* %out, align 8
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ret void
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}
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; SI-LABEL: @local_f64_store
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; SI-NOT: ADD
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; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
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define void @local_f64_store(double addrspace(3)* %out) nounwind {
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%gep = getelementptr double addrspace(3)* %out, i32 7
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store double 16.0, double addrspace(3)* %gep, align 8
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ret void
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}
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; SI-LABEL: @local_f64_store_0_offset
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; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
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define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
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store double 20.0, double addrspace(3)* %out, align 8
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ret void
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}
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; SI-LABEL: @local_v2i64_store
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; SI-NOT: ADD
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x78 [M0]
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x70 [M0]
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define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind {
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%gep = getelementptr <2 x i64> addrspace(3)* %out, i32 7
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store <2 x i64> <i64 5678, i64 5678>, <2 x i64> addrspace(3)* %gep, align 16
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ret void
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}
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; SI-LABEL: @local_v2i64_store_0_offset
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; SI-NOT: ADD
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
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define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
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store <2 x i64> <i64 1234, i64 1234>, <2 x i64> addrspace(3)* %out, align 16
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ret void
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}
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; SI-LABEL: @local_v4i64_store
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; SI-NOT: ADD
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf8 [M0]
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf0 [M0]
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe8 [M0]
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe0 [M0]
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define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind {
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%gep = getelementptr <4 x i64> addrspace(3)* %out, i32 7
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store <4 x i64> <i64 5678, i64 5678, i64 5678, i64 5678>, <4 x i64> addrspace(3)* %gep, align 16
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ret void
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}
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; SI-LABEL: @local_v4i64_store_0_offset
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; SI-NOT: ADD
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x18 [M0]
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x10 [M0]
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
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; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
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define void @local_v4i64_store_0_offset(<4 x i64> addrspace(3)* %out) nounwind {
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store <4 x i64> <i64 1234, i64 1234, i64 1234, i64 1234>, <4 x i64> addrspace(3)* %out, align 16
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ret void
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}
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