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For little endian, we need to make some straightforward adjustments in the code expansions for scalar_to_vector and vector_extract of v2f64. First, scalar_to_vector must place the scalar into vector element zero. However, our implementation of SUBREG_TO_REG will place it into big-element vector element zero (high-order bits), and for little endian we need it in the low-order bits. The LE implementation splats the high-order doubleword into the low-order doubleword. Second, the meaning of (vector_extract x, 0) and (vector_extract x, 1) must be reversed for similar reasons. A new test is added that tests code generation for insertelement and extractelement for both element 0 and element 1. It is disabled in this patch but enabled in patch 4/4, for reasons stated in the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223788 91177308-0d34-0410-b5e6-96231b3b80d8
941 lines
42 KiB
TableGen
941 lines
42 KiB
TableGen
//===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the VSX extension to the PowerPC instruction set.
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//
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//===----------------------------------------------------------------------===//
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def PPCRegVSRCAsmOperand : AsmOperandClass {
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let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber";
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}
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def vsrc : RegisterOperand<VSRC> {
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let ParserMatchClass = PPCRegVSRCAsmOperand;
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}
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def PPCRegVSFRCAsmOperand : AsmOperandClass {
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let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber";
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}
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def vsfrc : RegisterOperand<VSFRC> {
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let ParserMatchClass = PPCRegVSFRCAsmOperand;
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}
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// Little-endian-specific nodes.
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def SDT_PPClxvd2x : SDTypeProfile<1, 1, [
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SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
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]>;
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def SDT_PPCstxvd2x : SDTypeProfile<0, 2, [
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SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
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]>;
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def SDT_PPCxxswapd : SDTypeProfile<1, 1, [
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SDTCisSameAs<0, 1>
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]>;
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def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
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[SDNPHasChain, SDNPMayLoad]>;
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def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
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[SDNPHasChain, SDNPMayStore]>;
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def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
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multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, dag OOL, dag IOL,
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string asmbase, string asmstr, InstrItinClass itin,
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list<dag> pattern> {
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let BaseName = asmbase in {
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def NAME : XX3Form_Rc<opcode, xo, OOL, IOL,
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!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
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pattern>;
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let Defs = [CR6] in
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def o : XX3Form_Rc<opcode, xo, OOL, IOL,
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!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
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[]>, isDOT;
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}
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}
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def HasVSX : Predicate<"PPCSubTarget->hasVSX()">;
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def IsLittleEndian : Predicate<"PPCSubTarget->isLittleEndian()">;
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def IsBigEndian : Predicate<"!PPCSubTarget->isLittleEndian()">;
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let Predicates = [HasVSX] in {
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let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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let hasSideEffects = 0 in { // VSX instructions don't have side effects.
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let Uses = [RM] in {
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// Load indexed instructions
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let mayLoad = 1, canFoldAsLoad = 1 in {
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def LXSDX : XX1Form<31, 588,
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(outs vsfrc:$XT), (ins memrr:$src),
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"lxsdx $XT, $src", IIC_LdStLFD,
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[(set f64:$XT, (load xoaddr:$src))]>;
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def LXVD2X : XX1Form<31, 844,
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(outs vsrc:$XT), (ins memrr:$src),
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"lxvd2x $XT, $src", IIC_LdStLFD,
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[(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>;
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def LXVDSX : XX1Form<31, 332,
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(outs vsrc:$XT), (ins memrr:$src),
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"lxvdsx $XT, $src", IIC_LdStLFD, []>;
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def LXVW4X : XX1Form<31, 780,
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(outs vsrc:$XT), (ins memrr:$src),
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"lxvw4x $XT, $src", IIC_LdStLFD,
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[(set v4i32:$XT, (int_ppc_vsx_lxvw4x xoaddr:$src))]>;
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}
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// Store indexed instructions
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let mayStore = 1 in {
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def STXSDX : XX1Form<31, 716,
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(outs), (ins vsfrc:$XT, memrr:$dst),
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"stxsdx $XT, $dst", IIC_LdStSTFD,
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[(store f64:$XT, xoaddr:$dst)]>;
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def STXVD2X : XX1Form<31, 972,
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(outs), (ins vsrc:$XT, memrr:$dst),
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"stxvd2x $XT, $dst", IIC_LdStSTFD,
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[(int_ppc_vsx_stxvd2x v2f64:$XT, xoaddr:$dst)]>;
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def STXVW4X : XX1Form<31, 908,
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(outs), (ins vsrc:$XT, memrr:$dst),
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"stxvw4x $XT, $dst", IIC_LdStSTFD,
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[(int_ppc_vsx_stxvw4x v4i32:$XT, xoaddr:$dst)]>;
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}
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// Add/Mul Instructions
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let isCommutable = 1 in {
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def XSADDDP : XX3Form<60, 32,
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(outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
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"xsadddp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fadd f64:$XA, f64:$XB))]>;
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def XSMULDP : XX3Form<60, 48,
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(outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
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"xsmuldp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fmul f64:$XA, f64:$XB))]>;
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def XVADDDP : XX3Form<60, 96,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvadddp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fadd v2f64:$XA, v2f64:$XB))]>;
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def XVADDSP : XX3Form<60, 64,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvaddsp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fadd v4f32:$XA, v4f32:$XB))]>;
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def XVMULDP : XX3Form<60, 112,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvmuldp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fmul v2f64:$XA, v2f64:$XB))]>;
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def XVMULSP : XX3Form<60, 80,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvmulsp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fmul v4f32:$XA, v4f32:$XB))]>;
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}
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// Subtract Instructions
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def XSSUBDP : XX3Form<60, 40,
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(outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
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"xssubdp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fsub f64:$XA, f64:$XB))]>;
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def XVSUBDP : XX3Form<60, 104,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvsubdp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fsub v2f64:$XA, v2f64:$XB))]>;
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def XVSUBSP : XX3Form<60, 72,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvsubsp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fsub v4f32:$XA, v4f32:$XB))]>;
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// FMA Instructions
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let BaseName = "XSMADDADP" in {
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let isCommutable = 1 in
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def XSMADDADP : XX3Form<60, 33,
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(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
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"xsmaddadp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fma f64:$XA, f64:$XB, f64:$XTi))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XSMADDMDP : XX3Form<60, 41,
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(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
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"xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XSMSUBADP" in {
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let isCommutable = 1 in
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def XSMSUBADP : XX3Form<60, 49,
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(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
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"xsmsubadp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XSMSUBMDP : XX3Form<60, 57,
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(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
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"xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XSNMADDADP" in {
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let isCommutable = 1 in
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def XSNMADDADP : XX3Form<60, 161,
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(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
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"xsnmaddadp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, f64:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XSNMADDMDP : XX3Form<60, 169,
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(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
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"xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XSNMSUBADP" in {
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let isCommutable = 1 in
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def XSNMSUBADP : XX3Form<60, 177,
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(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
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"xsnmsubadp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XSNMSUBMDP : XX3Form<60, 185,
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(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
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"xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XVMADDADP" in {
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let isCommutable = 1 in
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def XVMADDADP : XX3Form<60, 97,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmaddadp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XVMADDMDP : XX3Form<60, 105,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XVMADDASP" in {
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let isCommutable = 1 in
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def XVMADDASP : XX3Form<60, 65,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmaddasp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XVMADDMSP : XX3Form<60, 73,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XVMSUBADP" in {
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let isCommutable = 1 in
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def XVMSUBADP : XX3Form<60, 113,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmsubadp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XVMSUBMDP : XX3Form<60, 121,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XVMSUBASP" in {
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let isCommutable = 1 in
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def XVMSUBASP : XX3Form<60, 81,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmsubasp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XVMSUBMSP : XX3Form<60, 89,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XVNMADDADP" in {
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let isCommutable = 1 in
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def XVNMADDADP : XX3Form<60, 225,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmaddadp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XVNMADDMDP : XX3Form<60, 233,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XVNMADDASP" in {
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let isCommutable = 1 in
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def XVNMADDASP : XX3Form<60, 193,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmaddasp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XVNMADDMSP : XX3Form<60, 201,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XVNMSUBADP" in {
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let isCommutable = 1 in
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def XVNMSUBADP : XX3Form<60, 241,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmsubadp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XVNMSUBMDP : XX3Form<60, 249,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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let BaseName = "XVNMSUBASP" in {
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let isCommutable = 1 in
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def XVNMSUBASP : XX3Form<60, 209,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmsubasp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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let IsVSXFMAAlt = 1 in
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def XVNMSUBMSP : XX3Form<60, 217,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
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AltVSXFMARel;
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}
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// Division Instructions
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def XSDIVDP : XX3Form<60, 56,
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(outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
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"xsdivdp $XT, $XA, $XB", IIC_FPDivD,
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[(set f64:$XT, (fdiv f64:$XA, f64:$XB))]>;
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def XSSQRTDP : XX2Form<60, 75,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xssqrtdp $XT, $XB", IIC_FPSqrtD,
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[(set f64:$XT, (fsqrt f64:$XB))]>;
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def XSREDP : XX2Form<60, 90,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsredp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfre f64:$XB))]>;
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def XSRSQRTEDP : XX2Form<60, 74,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsrsqrtedp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
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def XSTDIVDP : XX3Form_1<60, 61,
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(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
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"xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
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def XSTSQRTDP : XX2Form_1<60, 106,
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(outs crrc:$crD), (ins vsfrc:$XB),
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"xstsqrtdp $crD, $XB", IIC_FPCompare, []>;
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def XVDIVDP : XX3Form<60, 120,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvdivdp $XT, $XA, $XB", IIC_FPDivD,
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[(set v2f64:$XT, (fdiv v2f64:$XA, v2f64:$XB))]>;
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def XVDIVSP : XX3Form<60, 88,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvdivsp $XT, $XA, $XB", IIC_FPDivS,
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[(set v4f32:$XT, (fdiv v4f32:$XA, v4f32:$XB))]>;
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def XVSQRTDP : XX2Form<60, 203,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvsqrtdp $XT, $XB", IIC_FPSqrtD,
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[(set v2f64:$XT, (fsqrt v2f64:$XB))]>;
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def XVSQRTSP : XX2Form<60, 139,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvsqrtsp $XT, $XB", IIC_FPSqrtS,
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[(set v4f32:$XT, (fsqrt v4f32:$XB))]>;
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def XVTDIVDP : XX3Form_1<60, 125,
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(outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
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"xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
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def XVTDIVSP : XX3Form_1<60, 93,
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(outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
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"xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>;
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def XVTSQRTDP : XX2Form_1<60, 234,
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(outs crrc:$crD), (ins vsrc:$XB),
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"xvtsqrtdp $crD, $XB", IIC_FPCompare, []>;
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def XVTSQRTSP : XX2Form_1<60, 170,
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(outs crrc:$crD), (ins vsrc:$XB),
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"xvtsqrtsp $crD, $XB", IIC_FPCompare, []>;
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def XVREDP : XX2Form<60, 218,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvredp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (PPCfre v2f64:$XB))]>;
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def XVRESP : XX2Form<60, 154,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvresp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (PPCfre v4f32:$XB))]>;
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def XVRSQRTEDP : XX2Form<60, 202,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvrsqrtedp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>;
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def XVRSQRTESP : XX2Form<60, 138,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvrsqrtesp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>;
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// Compare Instructions
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def XSCMPODP : XX3Form_1<60, 43,
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(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
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"xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>;
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def XSCMPUDP : XX3Form_1<60, 35,
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(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
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"xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;
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defm XVCMPEQDP : XX3Form_Rcr<60, 99,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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defm XVCMPEQSP : XX3Form_Rcr<60, 67,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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defm XVCMPGEDP : XX3Form_Rcr<60, 115,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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defm XVCMPGESP : XX3Form_Rcr<60, 83,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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defm XVCMPGTDP : XX3Form_Rcr<60, 107,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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defm XVCMPGTSP : XX3Form_Rcr<60, 75,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
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// Move Instructions
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def XSABSDP : XX2Form<60, 345,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsabsdp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (fabs f64:$XB))]>;
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def XSNABSDP : XX2Form<60, 361,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsnabsdp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (fneg (fabs f64:$XB)))]>;
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def XSNEGDP : XX2Form<60, 377,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsnegdp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (fneg f64:$XB))]>;
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def XSCPSGNDP : XX3Form<60, 176,
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(outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
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"xscpsgndp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>;
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def XVABSDP : XX2Form<60, 473,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvabsdp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fabs v2f64:$XB))]>;
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def XVABSSP : XX2Form<60, 409,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvabssp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fabs v4f32:$XB))]>;
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def XVCPSGNDP : XX3Form<60, 240,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcpsgndp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>;
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def XVCPSGNSP : XX3Form<60, 208,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcpsgnsp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>;
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def XVNABSDP : XX2Form<60, 489,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvnabsdp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>;
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def XVNABSSP : XX2Form<60, 425,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvnabssp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>;
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def XVNEGDP : XX2Form<60, 505,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvnegdp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fneg v2f64:$XB))]>;
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def XVNEGSP : XX2Form<60, 441,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvnegsp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fneg v4f32:$XB))]>;
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// Conversion Instructions
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def XSCVDPSP : XX2Form<60, 265,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpsp $XT, $XB", IIC_VecFP, []>;
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def XSCVDPSXDS : XX2Form<60, 344,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpsxds $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfctidz f64:$XB))]>;
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def XSCVDPSXWS : XX2Form<60, 88,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpsxws $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfctiwz f64:$XB))]>;
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def XSCVDPUXDS : XX2Form<60, 328,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpuxds $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfctiduz f64:$XB))]>;
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def XSCVDPUXWS : XX2Form<60, 72,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpuxws $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfctiwuz f64:$XB))]>;
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def XSCVSPDP : XX2Form<60, 329,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvspdp $XT, $XB", IIC_VecFP, []>;
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def XSCVSXDDP : XX2Form<60, 376,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvsxddp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfcfid f64:$XB))]>;
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def XSCVUXDDP : XX2Form<60, 360,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvuxddp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfcfidu f64:$XB))]>;
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def XVCVDPSP : XX2Form<60, 393,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpsp $XT, $XB", IIC_VecFP, []>;
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def XVCVDPSXDS : XX2Form<60, 472,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpsxds $XT, $XB", IIC_VecFP,
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[(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
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def XVCVDPSXWS : XX2Form<60, 216,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpsxws $XT, $XB", IIC_VecFP, []>;
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def XVCVDPUXDS : XX2Form<60, 456,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpuxds $XT, $XB", IIC_VecFP,
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[(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
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def XVCVDPUXWS : XX2Form<60, 200,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpuxws $XT, $XB", IIC_VecFP, []>;
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def XVCVSPDP : XX2Form<60, 457,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspdp $XT, $XB", IIC_VecFP, []>;
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def XVCVSPSXDS : XX2Form<60, 408,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspsxds $XT, $XB", IIC_VecFP, []>;
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def XVCVSPSXWS : XX2Form<60, 152,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspsxws $XT, $XB", IIC_VecFP, []>;
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def XVCVSPUXDS : XX2Form<60, 392,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspuxds $XT, $XB", IIC_VecFP, []>;
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def XVCVSPUXWS : XX2Form<60, 136,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspuxws $XT, $XB", IIC_VecFP, []>;
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def XVCVSXDDP : XX2Form<60, 504,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxddp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
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def XVCVSXDSP : XX2Form<60, 440,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxdsp $XT, $XB", IIC_VecFP, []>;
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def XVCVSXWDP : XX2Form<60, 248,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxwdp $XT, $XB", IIC_VecFP, []>;
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def XVCVSXWSP : XX2Form<60, 184,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxwsp $XT, $XB", IIC_VecFP, []>;
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def XVCVUXDDP : XX2Form<60, 488,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxddp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
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def XVCVUXDSP : XX2Form<60, 424,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxdsp $XT, $XB", IIC_VecFP, []>;
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def XVCVUXWDP : XX2Form<60, 232,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxwdp $XT, $XB", IIC_VecFP, []>;
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def XVCVUXWSP : XX2Form<60, 168,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxwsp $XT, $XB", IIC_VecFP, []>;
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// Rounding Instructions
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def XSRDPI : XX2Form<60, 73,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsrdpi $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (frnd f64:$XB))]>;
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def XSRDPIC : XX2Form<60, 107,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsrdpic $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (fnearbyint f64:$XB))]>;
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def XSRDPIM : XX2Form<60, 121,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsrdpim $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (ffloor f64:$XB))]>;
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def XSRDPIP : XX2Form<60, 105,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsrdpip $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (fceil f64:$XB))]>;
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def XSRDPIZ : XX2Form<60, 89,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsrdpiz $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (ftrunc f64:$XB))]>;
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def XVRDPI : XX2Form<60, 201,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvrdpi $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (frnd v2f64:$XB))]>;
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def XVRDPIC : XX2Form<60, 235,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvrdpic $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fnearbyint v2f64:$XB))]>;
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def XVRDPIM : XX2Form<60, 249,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvrdpim $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (ffloor v2f64:$XB))]>;
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def XVRDPIP : XX2Form<60, 233,
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(outs vsrc:$XT), (ins vsrc:$XB),
|
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"xvrdpip $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fceil v2f64:$XB))]>;
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def XVRDPIZ : XX2Form<60, 217,
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(outs vsrc:$XT), (ins vsrc:$XB),
|
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"xvrdpiz $XT, $XB", IIC_VecFP,
|
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[(set v2f64:$XT, (ftrunc v2f64:$XB))]>;
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def XVRSPI : XX2Form<60, 137,
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(outs vsrc:$XT), (ins vsrc:$XB),
|
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"xvrspi $XT, $XB", IIC_VecFP,
|
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[(set v4f32:$XT, (frnd v4f32:$XB))]>;
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def XVRSPIC : XX2Form<60, 171,
|
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(outs vsrc:$XT), (ins vsrc:$XB),
|
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"xvrspic $XT, $XB", IIC_VecFP,
|
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[(set v4f32:$XT, (fnearbyint v4f32:$XB))]>;
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def XVRSPIM : XX2Form<60, 185,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
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"xvrspim $XT, $XB", IIC_VecFP,
|
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[(set v4f32:$XT, (ffloor v4f32:$XB))]>;
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def XVRSPIP : XX2Form<60, 169,
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(outs vsrc:$XT), (ins vsrc:$XB),
|
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"xvrspip $XT, $XB", IIC_VecFP,
|
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[(set v4f32:$XT, (fceil v4f32:$XB))]>;
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def XVRSPIZ : XX2Form<60, 153,
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(outs vsrc:$XT), (ins vsrc:$XB),
|
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"xvrspiz $XT, $XB", IIC_VecFP,
|
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[(set v4f32:$XT, (ftrunc v4f32:$XB))]>;
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|
|
// Max/Min Instructions
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let isCommutable = 1 in {
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def XSMAXDP : XX3Form<60, 160,
|
|
(outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
|
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"xsmaxdp $XT, $XA, $XB", IIC_VecFP,
|
|
[(set vsfrc:$XT,
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(int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>;
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def XSMINDP : XX3Form<60, 168,
|
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(outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
|
|
"xsmindp $XT, $XA, $XB", IIC_VecFP,
|
|
[(set vsfrc:$XT,
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(int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>;
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|
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def XVMAXDP : XX3Form<60, 224,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
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"xvmaxdp $XT, $XA, $XB", IIC_VecFP,
|
|
[(set vsrc:$XT,
|
|
(int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>;
|
|
def XVMINDP : XX3Form<60, 232,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmindp $XT, $XA, $XB", IIC_VecFP,
|
|
[(set vsrc:$XT,
|
|
(int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>;
|
|
|
|
def XVMAXSP : XX3Form<60, 192,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmaxsp $XT, $XA, $XB", IIC_VecFP,
|
|
[(set vsrc:$XT,
|
|
(int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>;
|
|
def XVMINSP : XX3Form<60, 200,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvminsp $XT, $XA, $XB", IIC_VecFP,
|
|
[(set vsrc:$XT,
|
|
(int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>;
|
|
} // isCommutable
|
|
} // Uses = [RM]
|
|
|
|
// Logical Instructions
|
|
let isCommutable = 1 in
|
|
def XXLAND : XX3Form<60, 130,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxland $XT, $XA, $XB", IIC_VecGeneral,
|
|
[(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>;
|
|
def XXLANDC : XX3Form<60, 138,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxlandc $XT, $XA, $XB", IIC_VecGeneral,
|
|
[(set v4i32:$XT, (and v4i32:$XA,
|
|
(vnot_ppc v4i32:$XB)))]>;
|
|
let isCommutable = 1 in {
|
|
def XXLNOR : XX3Form<60, 162,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxlnor $XT, $XA, $XB", IIC_VecGeneral,
|
|
[(set v4i32:$XT, (vnot_ppc (or v4i32:$XA,
|
|
v4i32:$XB)))]>;
|
|
def XXLOR : XX3Form<60, 146,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxlor $XT, $XA, $XB", IIC_VecGeneral,
|
|
[(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>;
|
|
let isCodeGenOnly = 1 in
|
|
def XXLORf: XX3Form<60, 146,
|
|
(outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
|
|
"xxlor $XT, $XA, $XB", IIC_VecGeneral, []>;
|
|
def XXLXOR : XX3Form<60, 154,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxlxor $XT, $XA, $XB", IIC_VecGeneral,
|
|
[(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
|
|
} // isCommutable
|
|
|
|
// Permutation Instructions
|
|
def XXMRGHW : XX3Form<60, 18,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>;
|
|
def XXMRGLW : XX3Form<60, 50,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>;
|
|
|
|
def XXPERMDI : XX3Form_2<60, 10,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
|
|
"xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, []>;
|
|
def XXSEL : XX4Form<60, 3,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
|
|
"xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
|
|
|
|
def XXSLDWI : XX3Form_2<60, 2,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
|
|
"xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, []>;
|
|
def XXSPLTW : XX2Form_2<60, 164,
|
|
(outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
|
|
"xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
|
|
} // hasSideEffects
|
|
|
|
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
|
|
// instruction selection into a branch sequence.
|
|
let usesCustomInserter = 1, // Expanded after instruction selection.
|
|
PPC970_Single = 1 in {
|
|
|
|
def SELECT_CC_VSRC: Pseudo<(outs vsrc:$dst),
|
|
(ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC),
|
|
"#SELECT_CC_VSRC",
|
|
[]>;
|
|
def SELECT_VSRC: Pseudo<(outs vsrc:$dst),
|
|
(ins crbitrc:$cond, vsrc:$T, vsrc:$F),
|
|
"#SELECT_VSRC",
|
|
[(set v2f64:$dst,
|
|
(select i1:$cond, v2f64:$T, v2f64:$F))]>;
|
|
def SELECT_CC_VSFRC: Pseudo<(outs f8rc:$dst),
|
|
(ins crrc:$cond, f8rc:$T, f8rc:$F,
|
|
i32imm:$BROPC), "#SELECT_CC_VSFRC",
|
|
[]>;
|
|
def SELECT_VSFRC: Pseudo<(outs f8rc:$dst),
|
|
(ins crbitrc:$cond, f8rc:$T, f8rc:$F),
|
|
"#SELECT_VSFRC",
|
|
[(set f64:$dst,
|
|
(select i1:$cond, f64:$T, f64:$F))]>;
|
|
} // usesCustomInserter
|
|
} // AddedComplexity
|
|
|
|
def : InstAlias<"xvmovdp $XT, $XB",
|
|
(XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
|
|
def : InstAlias<"xvmovsp $XT, $XB",
|
|
(XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
|
|
|
|
def : InstAlias<"xxspltd $XT, $XB, 0",
|
|
(XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>;
|
|
def : InstAlias<"xxspltd $XT, $XB, 1",
|
|
(XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>;
|
|
def : InstAlias<"xxmrghd $XT, $XA, $XB",
|
|
(XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>;
|
|
def : InstAlias<"xxmrgld $XT, $XA, $XB",
|
|
(XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>;
|
|
def : InstAlias<"xxswapd $XT, $XB",
|
|
(XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
|
|
|
|
let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
|
|
|
|
let Predicates = [IsBigEndian] in {
|
|
def : Pat<(v2f64 (scalar_to_vector f64:$A)),
|
|
(v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
|
|
|
|
def : Pat<(f64 (vector_extract v2f64:$S, 0)),
|
|
(f64 (EXTRACT_SUBREG $S, sub_64))>;
|
|
def : Pat<(f64 (vector_extract v2f64:$S, 1)),
|
|
(f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
|
|
}
|
|
|
|
let Predicates = [IsLittleEndian] in {
|
|
def : Pat<(v2f64 (scalar_to_vector f64:$A)),
|
|
(v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
|
|
(SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;
|
|
|
|
def : Pat<(f64 (vector_extract v2f64:$S, 0)),
|
|
(f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
|
|
def : Pat<(f64 (vector_extract v2f64:$S, 1)),
|
|
(f64 (EXTRACT_SUBREG $S, sub_64))>;
|
|
}
|
|
|
|
// Additional fnmsub patterns: -a*c + b == -(a*c - b)
|
|
def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
|
|
(XSNMSUBADP $B, $C, $A)>;
|
|
def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
|
|
(XSNMSUBADP $B, $C, $A)>;
|
|
|
|
def : Pat<(fma (fneg v2f64:$A), v2f64:$C, v2f64:$B),
|
|
(XVNMSUBADP $B, $C, $A)>;
|
|
def : Pat<(fma v2f64:$A, (fneg v2f64:$C), v2f64:$B),
|
|
(XVNMSUBADP $B, $C, $A)>;
|
|
|
|
def : Pat<(fma (fneg v4f32:$A), v4f32:$C, v4f32:$B),
|
|
(XVNMSUBASP $B, $C, $A)>;
|
|
def : Pat<(fma v4f32:$A, (fneg v4f32:$C), v4f32:$B),
|
|
(XVNMSUBASP $B, $C, $A)>;
|
|
|
|
def : Pat<(v2f64 (bitconvert v4f32:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
|
|
def : Pat<(v2f64 (bitconvert v4i32:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
|
|
def : Pat<(v2f64 (bitconvert v8i16:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
|
|
def : Pat<(v2f64 (bitconvert v16i8:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
|
|
|
|
def : Pat<(v4f32 (bitconvert v2f64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
def : Pat<(v4i32 (bitconvert v2f64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
def : Pat<(v8i16 (bitconvert v2f64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
def : Pat<(v16i8 (bitconvert v2f64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
|
|
def : Pat<(v2i64 (bitconvert v4f32:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
|
|
def : Pat<(v2i64 (bitconvert v4i32:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
|
|
def : Pat<(v2i64 (bitconvert v8i16:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
|
|
def : Pat<(v2i64 (bitconvert v16i8:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
|
|
|
|
def : Pat<(v4f32 (bitconvert v2i64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
def : Pat<(v4i32 (bitconvert v2i64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
def : Pat<(v8i16 (bitconvert v2i64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
def : Pat<(v16i8 (bitconvert v2i64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
|
|
def : Pat<(v2f64 (bitconvert v2i64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
def : Pat<(v2i64 (bitconvert v2f64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
|
|
// sign extension patterns
|
|
// To extend "in place" from v2i32 to v2i64, we have input data like:
|
|
// | undef | i32 | undef | i32 |
|
|
// but xvcvsxwdp expects the input in big-Endian format:
|
|
// | i32 | undef | i32 | undef |
|
|
// so we need to shift everything to the left by one i32 (word) before
|
|
// the conversion.
|
|
def : Pat<(sext_inreg v2i64:$C, v2i32),
|
|
(XVCVDPSXDS (XVCVSXWDP (XXSLDWI $C, $C, 1)))>;
|
|
def : Pat<(v2f64 (sint_to_fp (sext_inreg v2i64:$C, v2i32))),
|
|
(XVCVSXWDP (XXSLDWI $C, $C, 1))>;
|
|
|
|
// Loads.
|
|
def : Pat<(v2f64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
|
|
def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
|
|
def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>;
|
|
def : Pat<(v2f64 (PPClxvd2x xoaddr:$src)), (LXVD2X xoaddr:$src)>;
|
|
|
|
// Stores.
|
|
def : Pat<(store v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
|
|
def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
|
|
def : Pat<(store v4i32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
|
|
def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
|
|
|
|
// Permutes.
|
|
def : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>;
|
|
def : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>;
|
|
def : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>;
|
|
def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>;
|
|
|
|
// Selects.
|
|
def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)),
|
|
(SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
|
|
def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)),
|
|
(SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;
|
|
def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)),
|
|
(SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>;
|
|
def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)),
|
|
(SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;
|
|
def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)),
|
|
(SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
|
|
def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)),
|
|
(SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
|
|
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
|
|
(SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
|
|
(SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
|
|
(SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>;
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
|
|
(SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
|
|
(SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
|
|
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
|
|
(SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>;
|
|
|
|
// Divides.
|
|
def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),
|
|
(XVDIVSP $A, $B)>;
|
|
def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),
|
|
(XVDIVDP $A, $B)>;
|
|
|
|
} // AddedComplexity
|
|
} // HasVSX
|
|
|