mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
3b4b5367da
Allow LLVM to take advantage of shift instructions that set the ZF flag, making instructions that test the destination superfluous. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182454 91177308-0d34-0410-b5e6-96231b3b80d8
166 lines
3.5 KiB
LLVM
166 lines
3.5 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -show-mc-encoding | FileCheck %s
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define i32 @test1(i32 %X, i32* %y) nounwind {
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%tmp = load i32* %y ; <i32> [#uses=1]
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%tmp.upgrd.1 = icmp eq i32 %tmp, 0 ; <i1> [#uses=1]
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br i1 %tmp.upgrd.1, label %ReturnBlock, label %cond_true
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cond_true: ; preds = %0
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ret i32 1
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ReturnBlock: ; preds = %0
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ret i32 0
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; CHECK: test1:
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; CHECK: cmpl $0, (%rsi)
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}
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define i32 @test2(i32 %X, i32* %y) nounwind {
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%tmp = load i32* %y ; <i32> [#uses=1]
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%tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1]
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%tmp1.upgrd.2 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]
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br i1 %tmp1.upgrd.2, label %ReturnBlock, label %cond_true
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cond_true: ; preds = %0
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ret i32 1
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ReturnBlock: ; preds = %0
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ret i32 0
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; CHECK: test2:
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; CHECK: movl (%rsi), %eax
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; CHECK: shll $3, %eax
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; CHECK: testl %eax, %eax
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}
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define i64 @test3(i64 %x) nounwind {
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%t = icmp eq i64 %x, 0
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%r = zext i1 %t to i64
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ret i64 %r
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; CHECK: test3:
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; CHECK: testq %rdi, %rdi
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; CHECK: sete %al
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; CHECK: movzbl %al, %eax
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; CHECK: ret
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}
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define i64 @test4(i64 %x) nounwind {
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%t = icmp slt i64 %x, 1
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%r = zext i1 %t to i64
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ret i64 %r
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; CHECK: test4:
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; CHECK: testq %rdi, %rdi
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; CHECK: setle %al
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; CHECK: movzbl %al, %eax
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; CHECK: ret
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}
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define i32 @test5(double %A) nounwind {
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entry:
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%tmp2 = fcmp ogt double %A, 1.500000e+02; <i1> [#uses=1]
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%tmp5 = fcmp ult double %A, 7.500000e+01; <i1> [#uses=1]
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%bothcond = or i1 %tmp2, %tmp5; <i1> [#uses=1]
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br i1 %bothcond, label %bb8, label %bb12
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bb8:; preds = %entry
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%tmp9 = tail call i32 (...)* @foo( ) nounwind ; <i32> [#uses=1]
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ret i32 %tmp9
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bb12:; preds = %entry
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ret i32 32
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; CHECK: test5:
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; CHECK: ucomisd LCPI4_0(%rip), %xmm0
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; CHECK: ucomisd LCPI4_1(%rip), %xmm0
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}
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declare i32 @foo(...)
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define i32 @test6() nounwind align 2 {
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%A = alloca {i64, i64}, align 8
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%B = getelementptr inbounds {i64, i64}* %A, i64 0, i32 1
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%C = load i64* %B
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%D = icmp eq i64 %C, 0
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br i1 %D, label %T, label %F
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T:
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ret i32 1
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F:
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ret i32 0
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; CHECK: test6:
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; CHECK: cmpq $0, -8(%rsp)
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; CHECK: encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
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}
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; rdar://11866926
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define i32 @test7(i64 %res) nounwind {
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entry:
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; CHECK: test7:
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; CHECK-NOT: movabsq
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; CHECK: shrq $32, %rdi
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; CHECK: sete
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%lnot = icmp ult i64 %res, 4294967296
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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}
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define i32 @test8(i64 %res) nounwind {
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entry:
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; CHECK: test8:
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; CHECK-NOT: movabsq
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; CHECK: shrq $32, %rdi
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; CHECK: cmpq $3, %rdi
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%lnot = icmp ult i64 %res, 12884901888
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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}
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define i32 @test9(i64 %res) nounwind {
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entry:
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; CHECK: test9:
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; CHECK-NOT: movabsq
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; CHECK: shrq $33, %rdi
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; CHECK: sete
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%lnot = icmp ult i64 %res, 8589934592
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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}
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define i32 @test10(i64 %res) nounwind {
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entry:
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; CHECK: test10:
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; CHECK-NOT: movabsq
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; CHECK: shrq $32, %rdi
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; CHECK: setne
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%lnot = icmp uge i64 %res, 4294967296
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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}
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; rdar://9758774
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define i32 @test11(i64 %l) nounwind {
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entry:
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; CHECK: test11:
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; CHECK-NOT: movabsq
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; CHECK-NOT: andq
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; CHECK: shrq $47, %rdi
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; CHECK: cmpq $1, %rdi
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%shr.mask = and i64 %l, -140737488355328
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%cmp = icmp eq i64 %shr.mask, 140737488355328
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @test12() uwtable ssp {
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; CHECK: test12:
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; CHECK: testb
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%1 = call zeroext i1 @test12b()
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br i1 %1, label %2, label %3
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; <label>:2 ; preds = %0
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ret i32 1
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; <label>:3 ; preds = %0
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ret i32 2
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}
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declare zeroext i1 @test12b()
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