mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
294 lines
12 KiB
TableGen
294 lines
12 KiB
TableGen
//===- ARM64InstrAtomics.td - ARM64 Atomic codegen support -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// ARM64 Atomic operand code-gen constructs.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------
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// Atomic fences
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//===----------------------------------
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def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
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def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
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//===----------------------------------
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// Atomic loads
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//===----------------------------------
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// When they're actually atomic, only one addressing mode (GPR64sp) is
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// supported, but when they're relaxed and anything can be used, all the
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// standard modes would be valid and may give efficiency gains.
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// A atomic load operation that actually needs acquire semantics.
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class acquiring_load<PatFrag base>
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: PatFrag<(ops node:$ptr), (base node:$ptr), [{
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AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
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assert(Ordering != AcquireRelease && "unexpected load ordering");
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return Ordering == Acquire || Ordering == SequentiallyConsistent;
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}]>;
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// An atomic load operation that does not need either acquire or release
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// semantics.
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class relaxed_load<PatFrag base>
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: PatFrag<(ops node:$ptr), (base node:$ptr), [{
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AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
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return Ordering == Monotonic || Ordering == Unordered;
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}]>;
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// 8-bit loads
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def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
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def : Pat<(relaxed_load<atomic_load_8> ro_indexed8:$addr),
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(LDRBBro ro_indexed8:$addr)>;
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def : Pat<(relaxed_load<atomic_load_8> am_indexed8:$addr),
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(LDRBBui am_indexed8:$addr)>;
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def : Pat<(relaxed_load<atomic_load_8> am_unscaled8:$addr),
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(LDURBBi am_unscaled8:$addr)>;
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// 16-bit loads
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def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
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def : Pat<(relaxed_load<atomic_load_16> ro_indexed16:$addr),
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(LDRHHro ro_indexed16:$addr)>;
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def : Pat<(relaxed_load<atomic_load_16> am_indexed16:$addr),
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(LDRHHui am_indexed16:$addr)>;
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def : Pat<(relaxed_load<atomic_load_16> am_unscaled16:$addr),
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(LDURHHi am_unscaled16:$addr)>;
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// 32-bit loads
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def : Pat<(acquiring_load<atomic_load_32> GPR64sp:$ptr), (LDARW GPR64sp:$ptr)>;
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def : Pat<(relaxed_load<atomic_load_32> ro_indexed32:$addr),
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(LDRWro ro_indexed32:$addr)>;
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def : Pat<(relaxed_load<atomic_load_32> am_indexed32:$addr),
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(LDRWui am_indexed32:$addr)>;
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def : Pat<(relaxed_load<atomic_load_32> am_unscaled32:$addr),
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(LDURWi am_unscaled32:$addr)>;
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// 64-bit loads
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def : Pat<(acquiring_load<atomic_load_64> GPR64sp:$ptr), (LDARX GPR64sp:$ptr)>;
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def : Pat<(relaxed_load<atomic_load_64> ro_indexed64:$addr),
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(LDRXro ro_indexed64:$addr)>;
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def : Pat<(relaxed_load<atomic_load_64> am_indexed64:$addr),
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(LDRXui am_indexed64:$addr)>;
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def : Pat<(relaxed_load<atomic_load_64> am_unscaled64:$addr),
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(LDURXi am_unscaled64:$addr)>;
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//===----------------------------------
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// Atomic stores
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//===----------------------------------
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// When they're actually atomic, only one addressing mode (GPR64sp) is
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// supported, but when they're relaxed and anything can be used, all the
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// standard modes would be valid and may give efficiency gains.
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// A store operation that actually needs release semantics.
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class releasing_store<PatFrag base>
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: PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
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AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
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assert(Ordering != AcquireRelease && "unexpected store ordering");
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return Ordering == Release || Ordering == SequentiallyConsistent;
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}]>;
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// An atomic store operation that doesn't actually need to be atomic on ARM64.
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class relaxed_store<PatFrag base>
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: PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
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AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
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return Ordering == Monotonic || Ordering == Unordered;
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}]>;
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// 8-bit stores
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def : Pat<(releasing_store<atomic_store_8> GPR64sp:$ptr, GPR32:$val),
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(STLRB GPR32:$val, GPR64sp:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_8> ro_indexed8:$ptr, GPR32:$val),
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(STRBBro GPR32:$val, ro_indexed8:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_8> am_indexed8:$ptr, GPR32:$val),
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(STRBBui GPR32:$val, am_indexed8:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_8> am_unscaled8:$ptr, GPR32:$val),
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(STURBBi GPR32:$val, am_unscaled8:$ptr)>;
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// 16-bit stores
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def : Pat<(releasing_store<atomic_store_16> GPR64sp:$ptr, GPR32:$val),
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(STLRH GPR32:$val, GPR64sp:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_16> ro_indexed16:$ptr, GPR32:$val),
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(STRHHro GPR32:$val, ro_indexed16:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_16> am_indexed16:$ptr, GPR32:$val),
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(STRHHui GPR32:$val, am_indexed16:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_16> am_unscaled16:$ptr, GPR32:$val),
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(STURHHi GPR32:$val, am_unscaled16:$ptr)>;
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// 32-bit stores
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def : Pat<(releasing_store<atomic_store_32> GPR64sp:$ptr, GPR32:$val),
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(STLRW GPR32:$val, GPR64sp:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_32> ro_indexed32:$ptr, GPR32:$val),
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(STRWro GPR32:$val, ro_indexed32:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_32> am_indexed32:$ptr, GPR32:$val),
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(STRWui GPR32:$val, am_indexed32:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_32> am_unscaled32:$ptr, GPR32:$val),
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(STURWi GPR32:$val, am_unscaled32:$ptr)>;
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// 64-bit stores
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def : Pat<(releasing_store<atomic_store_64> GPR64sp:$ptr, GPR64:$val),
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(STLRX GPR64:$val, GPR64sp:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_64> ro_indexed64:$ptr, GPR64:$val),
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(STRXro GPR64:$val, ro_indexed64:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_64> am_indexed64:$ptr, GPR64:$val),
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(STRXui GPR64:$val, am_indexed64:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_64> am_unscaled64:$ptr, GPR64:$val),
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(STURXi GPR64:$val, am_unscaled64:$ptr)>;
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//===----------------------------------
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// Atomic read-modify-write operations
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//===----------------------------------
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// More complicated operations need lots of C++ support, so we just create
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// skeletons here for the C++ code to refer to.
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let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in {
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multiclass AtomicSizes {
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def _I8 : Pseudo<(outs GPR32:$dst),
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(ins GPR64sp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
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def _I16 : Pseudo<(outs GPR32:$dst),
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(ins GPR64sp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
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def _I32 : Pseudo<(outs GPR32:$dst),
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(ins GPR64sp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
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def _I64 : Pseudo<(outs GPR64:$dst),
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(ins GPR64sp:$ptr, GPR64:$incr, i32imm:$ordering), []>;
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def _I128 : Pseudo<(outs GPR64:$dstlo, GPR64:$dsthi),
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(ins GPR64sp:$ptr, GPR64:$incrlo, GPR64:$incrhi,
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i32imm:$ordering), []>;
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}
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}
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defm ATOMIC_LOAD_ADD : AtomicSizes;
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defm ATOMIC_LOAD_SUB : AtomicSizes;
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defm ATOMIC_LOAD_AND : AtomicSizes;
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defm ATOMIC_LOAD_OR : AtomicSizes;
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defm ATOMIC_LOAD_XOR : AtomicSizes;
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defm ATOMIC_LOAD_NAND : AtomicSizes;
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defm ATOMIC_SWAP : AtomicSizes;
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let Defs = [CPSR] in {
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// These operations need a CMP to calculate the correct value
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defm ATOMIC_LOAD_MIN : AtomicSizes;
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defm ATOMIC_LOAD_MAX : AtomicSizes;
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defm ATOMIC_LOAD_UMIN : AtomicSizes;
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defm ATOMIC_LOAD_UMAX : AtomicSizes;
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}
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class AtomicCmpSwap<RegisterClass GPRData>
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: Pseudo<(outs GPRData:$dst),
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(ins GPR64sp:$ptr, GPRData:$old, GPRData:$new,
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i32imm:$ordering), []> {
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let usesCustomInserter = 1;
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let hasCtrlDep = 1;
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let mayLoad = 1;
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let mayStore = 1;
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let Defs = [CPSR];
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}
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def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>;
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def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>;
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def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>;
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def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>;
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def ATOMIC_CMP_SWAP_I128
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: Pseudo<(outs GPR64:$dstlo, GPR64:$dsthi),
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(ins GPR64sp:$ptr, GPR64:$oldlo, GPR64:$oldhi,
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GPR64:$newlo, GPR64:$newhi, i32imm:$ordering), []> {
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let usesCustomInserter = 1;
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let hasCtrlDep = 1;
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let mayLoad = 1;
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let mayStore = 1;
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let Defs = [CPSR];
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}
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//===----------------------------------
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// Low-level exclusive operations
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//===----------------------------------
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// Load-exclusives.
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def ldxr_1 : PatFrag<(ops node:$ptr), (int_arm64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def ldxr_2 : PatFrag<(ops node:$ptr), (int_arm64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def ldxr_4 : PatFrag<(ops node:$ptr), (int_arm64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def ldxr_8 : PatFrag<(ops node:$ptr), (int_arm64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def : Pat<(ldxr_1 am_noindex:$addr),
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(SUBREG_TO_REG (i64 0), (LDXRB am_noindex:$addr), sub_32)>;
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def : Pat<(ldxr_2 am_noindex:$addr),
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(SUBREG_TO_REG (i64 0), (LDXRH am_noindex:$addr), sub_32)>;
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def : Pat<(ldxr_4 am_noindex:$addr),
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(SUBREG_TO_REG (i64 0), (LDXRW am_noindex:$addr), sub_32)>;
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def : Pat<(ldxr_8 am_noindex:$addr), (LDXRX am_noindex:$addr)>;
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def : Pat<(and (ldxr_1 am_noindex:$addr), 0xff),
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(SUBREG_TO_REG (i64 0), (LDXRB am_noindex:$addr), sub_32)>;
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def : Pat<(and (ldxr_2 am_noindex:$addr), 0xffff),
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(SUBREG_TO_REG (i64 0), (LDXRH am_noindex:$addr), sub_32)>;
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def : Pat<(and (ldxr_4 am_noindex:$addr), 0xffffffff),
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(SUBREG_TO_REG (i64 0), (LDXRW am_noindex:$addr), sub_32)>;
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// Store-exclusives.
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def stxr_1 : PatFrag<(ops node:$val, node:$ptr),
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(int_arm64_stxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def stxr_2 : PatFrag<(ops node:$val, node:$ptr),
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(int_arm64_stxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def stxr_4 : PatFrag<(ops node:$val, node:$ptr),
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(int_arm64_stxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def stxr_8 : PatFrag<(ops node:$val, node:$ptr),
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(int_arm64_stxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def : Pat<(stxr_1 GPR64:$val, am_noindex:$addr),
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(STXRB (EXTRACT_SUBREG GPR64:$val, sub_32), am_noindex:$addr)>;
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def : Pat<(stxr_2 GPR64:$val, am_noindex:$addr),
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(STXRH (EXTRACT_SUBREG GPR64:$val, sub_32), am_noindex:$addr)>;
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def : Pat<(stxr_4 GPR64:$val, am_noindex:$addr),
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(STXRW (EXTRACT_SUBREG GPR64:$val, sub_32), am_noindex:$addr)>;
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def : Pat<(stxr_8 GPR64:$val, am_noindex:$addr),
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(STXRX GPR64:$val, am_noindex:$addr)>;
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def : Pat<(stxr_1 (zext (and GPR32:$val, 0xff)), am_noindex:$addr),
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(STXRB GPR32:$val, am_noindex:$addr)>;
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def : Pat<(stxr_2 (zext (and GPR32:$val, 0xffff)), am_noindex:$addr),
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(STXRH GPR32:$val, am_noindex:$addr)>;
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def : Pat<(stxr_4 (zext GPR32:$val), am_noindex:$addr),
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(STXRW GPR32:$val, am_noindex:$addr)>;
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def : Pat<(stxr_1 (and GPR64:$val, 0xff), am_noindex:$addr),
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(STXRB (EXTRACT_SUBREG GPR64:$val, sub_32), am_noindex:$addr)>;
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def : Pat<(stxr_2 (and GPR64:$val, 0xffff), am_noindex:$addr),
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(STXRH (EXTRACT_SUBREG GPR64:$val, sub_32), am_noindex:$addr)>;
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def : Pat<(stxr_4 (and GPR64:$val, 0xffffffff), am_noindex:$addr),
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(STXRW (EXTRACT_SUBREG GPR64:$val, sub_32), am_noindex:$addr)>;
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// And clear exclusive.
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def : Pat<(int_arm64_clrex), (CLREX 0xf)>;
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