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5bafff36c7
This is still a work in progress but most of the NEON instruction set is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
930 B
LLVM
23 lines
930 B
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vqdmlsl\\.s16} %t | count 1
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; RUN: grep {vqdmlsl\\.s32} %t | count 1
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define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = load <4 x i16>* %C
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%tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = load <2 x i32>* %C
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%tmp4 = call <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
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ret <2 x i64> %tmp4
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}
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declare <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
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