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https://github.com/c64scene-ar/llvm-6502.git
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461f1fc359
The theory is it's still faster than a pair of movq / a quad of movl. This will probably hurt older chips like P4 but should run faster on current and future Intel processors. rdar://8817010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122955 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
1.2 KiB
LLVM
25 lines
1.2 KiB
LLVM
; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=nehalem | FileCheck %s
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define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 }* byval align 4 %z) nounwind {
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entry:
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; CHECK: ccosl:
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; CHECK: movaps
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; CHECK: movaps
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; CHECK: movups
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; CHECK: movups
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%iz = alloca { x86_fp80, x86_fp80 } ; <{ x86_fp80, x86_fp80 }*> [#uses=3]
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%tmp1 = getelementptr { x86_fp80, x86_fp80 }* %z, i32 0, i32 1 ; <x86_fp80*> [#uses=1]
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%tmp2 = load x86_fp80* %tmp1, align 16 ; <x86_fp80> [#uses=1]
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%tmp3 = fsub x86_fp80 0xK80000000000000000000, %tmp2 ; <x86_fp80> [#uses=1]
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%tmp4 = getelementptr { x86_fp80, x86_fp80 }* %iz, i32 0, i32 1 ; <x86_fp80*> [#uses=1]
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%real = getelementptr { x86_fp80, x86_fp80 }* %iz, i32 0, i32 0 ; <x86_fp80*> [#uses=1]
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%tmp6 = getelementptr { x86_fp80, x86_fp80 }* %z, i32 0, i32 0 ; <x86_fp80*> [#uses=1]
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%tmp7 = load x86_fp80* %tmp6, align 16 ; <x86_fp80> [#uses=1]
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store x86_fp80 %tmp3, x86_fp80* %real, align 16
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store x86_fp80 %tmp7, x86_fp80* %tmp4, align 16
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call void @ccoshl( { x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 }* byval align 4 %iz ) nounwind
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ret void
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}
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declare void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret , { x86_fp80, x86_fp80 }* byval align 4 ) nounwind
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