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https://github.com/c64scene-ar/llvm-6502.git
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b52bf6a3b3
All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
62 lines
2.1 KiB
LLVM
62 lines
2.1 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK-LABEL: @fneg
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; R600-CHECK: -PV
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; SI-CHECK-LABEL: @fneg
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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define void @fneg(float addrspace(1)* %out, float %in) {
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entry:
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%0 = fsub float -0.000000e+00, %in
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store float %0, float addrspace(1)* %out
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ret void
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}
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; R600-CHECK-LABEL: @fneg_v2
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; R600-CHECK: -PV
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; R600-CHECK: -PV
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; SI-CHECK-LABEL: @fneg_v2
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
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entry:
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%0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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; R600-CHECK-LABEL: @fneg_v4
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; R600-CHECK: -PV
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; R600-CHECK: -T
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; R600-CHECK: -PV
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; R600-CHECK: -PV
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; SI-CHECK-LABEL: @fneg_v4
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
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define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
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entry:
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%0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
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store <4 x float> %0, <4 x float> addrspace(1)* %out
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ret void
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}
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; DAGCombiner will transform:
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; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
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; unless the target returns true for isNegFree()
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; R600-CHECK-LABEL: @fneg_free
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; R600-CHECK-NOT: XOR
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; R600-CHECK: -KC0[2].Z
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; SI-CHECK-LABEL: @fneg_free
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; XXX: We could use V_ADD_F32_e64 with the negate bit here instead.
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; SI-CHECK: V_SUB_F32_e64 v{{[0-9]}}, 0.000000e+00, s{{[0-9]}}, 0, 0, 0, 0
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define void @fneg_free(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = bitcast i32 %in to float
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%1 = fsub float 0.0, %0
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store float %1, float addrspace(1)* %out
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ret void
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}
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