Tim Northover 2a83cb71ad AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed ... Sometimes we need emit the bits that would actually be a MOVN when producing a relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got wrong until now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206289 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-15 14:00:15 +00:00
..
adr.s	[ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types	2014-04-09 14:44:12 +00:00
advsimd.s
aliases.s	[ARM64] Add missing shifted register MVN alias to ORN	2014-04-09 14:44:26 +00:00
arithmetic-encoding.s
arm64-fixup.s
basic-a64-instructions.s
bitfield-encoding.s
branch-encoding.s	[ARM64] Conditional branches must always print their condition code, even AL.	2014-04-09 14:44:39 +00:00
crypto.s
diags.s
directive_loh.s
elf-relocs.s
fp-encoding.s	[ARM64] Properly support both apple and standard syntax for FMOV	2014-04-09 14:44:49 +00:00
large-relocs.s	AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed	2014-04-15 14:00:15 +00:00
lit.local.cfg
logical-encoding.s
mapping-across-sections.s
mapping-within-section.s
memory.s
nv-cond.s
optional-hash.s	Optional hash symbol feature support for ARM64	2014-04-15 11:43:09 +00:00
separator.s	Fix some doc and comment typos	2014-04-09 14:47:27 +00:00
simd-ldst.s
small-data-fixups.s
spsel-sysreg.s
system-encoding.s
tls-modifiers-darwin.s
tls-relocs.s
variable-exprs.s
vector-lists.s
verbose-vector-case.s