mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-21 00:32:23 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
424 lines
9.8 KiB
LLVM
424 lines
9.8 KiB
LLVM
; RUN: llc < %s -stress-early-ifcvt -aarch64-atomic-cfg-tidy=0 | FileCheck %s
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target triple = "arm64-apple-macosx"
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; CHECK: mm2
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define i32 @mm2(i32* nocapture %p, i32 %n) nounwind uwtable readonly ssp {
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entry:
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br label %do.body
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; CHECK: do.body
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; Loop body has no branches before the backedge.
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; CHECK-NOT: LBB
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do.body:
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%max.0 = phi i32 [ 0, %entry ], [ %max.1, %do.cond ]
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%min.0 = phi i32 [ 0, %entry ], [ %min.1, %do.cond ]
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%n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %do.cond ]
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%p.addr.0 = phi i32* [ %p, %entry ], [ %incdec.ptr, %do.cond ]
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%incdec.ptr = getelementptr inbounds i32, i32* %p.addr.0, i64 1
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%0 = load i32, i32* %p.addr.0, align 4
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%cmp = icmp sgt i32 %0, %max.0
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br i1 %cmp, label %do.cond, label %if.else
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if.else:
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%cmp1 = icmp slt i32 %0, %min.0
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%.min.0 = select i1 %cmp1, i32 %0, i32 %min.0
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br label %do.cond
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do.cond:
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%max.1 = phi i32 [ %0, %do.body ], [ %max.0, %if.else ]
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%min.1 = phi i32 [ %min.0, %do.body ], [ %.min.0, %if.else ]
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; CHECK: cbnz
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%dec = add i32 %n.addr.0, -1
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %do.end, label %do.body
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do.end:
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%sub = sub nsw i32 %max.1, %min.1
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ret i32 %sub
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}
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; CHECK-LABEL: fold_inc_true_32:
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; CHECK: {{subs.*wzr,|cmp}} w2, #1
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; CHECK-NEXT: csinc w0, w1, w0, eq
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; CHECK-NEXT: ret
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define i32 @fold_inc_true_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i32 %c, 1
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%inc = add nsw i32 %x, 1
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i32 [ %y, %eq_bb ], [ %inc, %entry ]
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ret i32 %cond
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}
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; CHECK-LABEL: fold_inc_true_64:
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; CHECK: {{subs.*xzr,|cmp}} x2, #1
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; CHECK-NEXT: csinc x0, x1, x0, eq
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; CHECK-NEXT: ret
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define i64 @fold_inc_true_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i64 %c, 1
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%inc = add nsw i64 %x, 1
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i64 [ %y, %eq_bb ], [ %inc, %entry ]
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ret i64 %cond
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}
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; CHECK-LABEL: fold_inc_false_32:
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; CHECK: {{subs.*wzr,|cmp}} w2, #1
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; CHECK-NEXT: csinc w0, w1, w0, ne
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; CHECK-NEXT: ret
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define i32 @fold_inc_false_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i32 %c, 1
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%inc = add nsw i32 %x, 1
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i32 [ %inc, %eq_bb ], [ %y, %entry ]
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ret i32 %cond
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}
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; CHECK-LABEL: fold_inc_false_64:
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; CHECK: {{subs.*xzr,|cmp}} x2, #1
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; CHECK-NEXT: csinc x0, x1, x0, ne
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; CHECK-NEXT: ret
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define i64 @fold_inc_false_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i64 %c, 1
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%inc = add nsw i64 %x, 1
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i64 [ %inc, %eq_bb ], [ %y, %entry ]
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ret i64 %cond
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}
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; CHECK-LABEL: fold_inv_true_32:
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; CHECK: {{subs.*wzr,|cmp}} w2, #1
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; CHECK-NEXT: csinv w0, w1, w0, eq
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; CHECK-NEXT: ret
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define i32 @fold_inv_true_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i32 %c, 1
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%inv = xor i32 %x, -1
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i32 [ %y, %eq_bb ], [ %inv, %entry ]
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ret i32 %cond
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}
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; CHECK-LABEL: fold_inv_true_64:
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; CHECK: {{subs.*xzr,|cmp}} x2, #1
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; CHECK-NEXT: csinv x0, x1, x0, eq
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; CHECK-NEXT: ret
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define i64 @fold_inv_true_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i64 %c, 1
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%inv = xor i64 %x, -1
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i64 [ %y, %eq_bb ], [ %inv, %entry ]
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ret i64 %cond
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}
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; CHECK-LABEL: fold_inv_false_32:
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; CHECK: {{subs.*wzr,|cmp}} w2, #1
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; CHECK-NEXT: csinv w0, w1, w0, ne
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; CHECK-NEXT: ret
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define i32 @fold_inv_false_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i32 %c, 1
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%inv = xor i32 %x, -1
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i32 [ %inv, %eq_bb ], [ %y, %entry ]
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ret i32 %cond
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}
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; CHECK-LABEL: fold_inv_false_64:
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; CHECK: {{subs.*xzr,|cmp}} x2, #1
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; CHECK-NEXT: csinv x0, x1, x0, ne
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; CHECK-NEXT: ret
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define i64 @fold_inv_false_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i64 %c, 1
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%inv = xor i64 %x, -1
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i64 [ %inv, %eq_bb ], [ %y, %entry ]
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ret i64 %cond
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}
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; CHECK-LABEL: fold_neg_true_32:
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; CHECK: {{subs.*wzr,|cmp}} w2, #1
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; CHECK-NEXT: csneg w0, w1, w0, eq
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; CHECK-NEXT: ret
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define i32 @fold_neg_true_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i32 %c, 1
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%neg = sub nsw i32 0, %x
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i32 [ %y, %eq_bb ], [ %neg, %entry ]
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ret i32 %cond
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}
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; CHECK-LABEL: fold_neg_true_64:
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; CHECK: {{subs.*xzr,|cmp}} x2, #1
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; CHECK-NEXT: csneg x0, x1, x0, eq
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; CHECK-NEXT: ret
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define i64 @fold_neg_true_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i64 %c, 1
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%neg = sub nsw i64 0, %x
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i64 [ %y, %eq_bb ], [ %neg, %entry ]
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ret i64 %cond
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}
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; CHECK-LABEL: fold_neg_false_32:
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; CHECK: {{subs.*wzr,|cmp}} w2, #1
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; CHECK-NEXT: csneg w0, w1, w0, ne
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; CHECK-NEXT: ret
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define i32 @fold_neg_false_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i32 %c, 1
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%neg = sub nsw i32 0, %x
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i32 [ %neg, %eq_bb ], [ %y, %entry ]
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ret i32 %cond
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}
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; CHECK-LABEL: fold_neg_false_64:
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; CHECK: {{subs.*xzr,|cmp}} x2, #1
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; CHECK-NEXT: csneg x0, x1, x0, ne
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; CHECK-NEXT: ret
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define i64 @fold_neg_false_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i64 %c, 1
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%neg = sub nsw i64 0, %x
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i64 [ %neg, %eq_bb ], [ %y, %entry ]
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ret i64 %cond
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}
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; CHECK: cbnz_32
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; CHECK: {{subs.*wzr,|cmp}} w2, #0
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; CHECK-NEXT: csel w0, w1, w0, ne
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; CHECK-NEXT: ret
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define i32 @cbnz_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i32 %c, 0
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i32 [ %x, %eq_bb ], [ %y, %entry ]
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ret i32 %cond
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}
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; CHECK: cbnz_64
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; CHECK: {{subs.*xzr,|cmp}} x2, #0
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; CHECK-NEXT: csel x0, x1, x0, ne
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; CHECK-NEXT: ret
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define i64 @cbnz_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
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entry:
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%tobool = icmp eq i64 %c, 0
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i64 [ %x, %eq_bb ], [ %y, %entry ]
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ret i64 %cond
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}
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; CHECK: cbz_32
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; CHECK: {{subs.*wzr,|cmp}} w2, #0
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; CHECK-NEXT: csel w0, w1, w0, eq
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; CHECK-NEXT: ret
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define i32 @cbz_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
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entry:
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%tobool = icmp ne i32 %c, 0
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br i1 %tobool, label %ne_bb, label %done
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ne_bb:
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br label %done
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done:
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%cond = phi i32 [ %x, %ne_bb ], [ %y, %entry ]
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ret i32 %cond
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}
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; CHECK: cbz_64
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; CHECK: {{subs.*xzr,|cmp}} x2, #0
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; CHECK-NEXT: csel x0, x1, x0, eq
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; CHECK-NEXT: ret
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define i64 @cbz_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
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entry:
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%tobool = icmp ne i64 %c, 0
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br i1 %tobool, label %ne_bb, label %done
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ne_bb:
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br label %done
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done:
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%cond = phi i64 [ %x, %ne_bb ], [ %y, %entry ]
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ret i64 %cond
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}
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; CHECK: tbnz_32
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; CHECK: {{ands.*xzr,|tst}} w2, #0x80
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; CHECK-NEXT: csel w0, w1, w0, ne
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; CHECK-NEXT: ret
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define i32 @tbnz_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
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entry:
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%mask = and i32 %c, 128
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%tobool = icmp eq i32 %mask, 0
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i32 [ %x, %eq_bb ], [ %y, %entry ]
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ret i32 %cond
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}
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; CHECK: tbnz_64
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; CHECK: {{ands.*xzr,|tst}} x2, #0x8000000000000000
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; CHECK-NEXT: csel x0, x1, x0, ne
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; CHECK-NEXT: ret
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define i64 @tbnz_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
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entry:
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%mask = and i64 %c, 9223372036854775808
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%tobool = icmp eq i64 %mask, 0
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br i1 %tobool, label %eq_bb, label %done
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eq_bb:
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br label %done
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done:
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%cond = phi i64 [ %x, %eq_bb ], [ %y, %entry ]
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ret i64 %cond
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}
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; CHECK: tbz_32
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; CHECK: {{ands.*xzr,|tst}} w2, #0x80
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; CHECK-NEXT: csel w0, w1, w0, eq
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; CHECK-NEXT: ret
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define i32 @tbz_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
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entry:
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%mask = and i32 %c, 128
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%tobool = icmp ne i32 %mask, 0
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br i1 %tobool, label %ne_bb, label %done
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ne_bb:
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br label %done
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done:
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%cond = phi i32 [ %x, %ne_bb ], [ %y, %entry ]
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ret i32 %cond
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}
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; CHECK: tbz_64
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; CHECK: {{ands.*xzr,|tst}} x2, #0x8000000000000000
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; CHECK-NEXT: csel x0, x1, x0, eq
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; CHECK-NEXT: ret
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define i64 @tbz_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
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entry:
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%mask = and i64 %c, 9223372036854775808
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%tobool = icmp ne i64 %mask, 0
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br i1 %tobool, label %ne_bb, label %done
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ne_bb:
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br label %done
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done:
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%cond = phi i64 [ %x, %ne_bb ], [ %y, %entry ]
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ret i64 %cond
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}
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; This function from 175.vpr folds an ADDWri into a CSINC.
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; Remember to clear the kill flag on the ADDWri.
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define i32 @get_ytrack_to_xtracks() nounwind ssp {
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entry:
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br label %for.body
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for.body:
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%x0 = load i32, i32* undef, align 4
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br i1 undef, label %if.then.i146, label %is_sbox.exit155
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if.then.i146:
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%add8.i143 = add nsw i32 0, %x0
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%rem.i144 = srem i32 %add8.i143, %x0
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%add9.i145 = add i32 %rem.i144, 1
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br label %is_sbox.exit155
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is_sbox.exit155: ; preds = %if.then.i146, %for.body
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%seg_offset.0.i151 = phi i32 [ %add9.i145, %if.then.i146 ], [ undef, %for.body ]
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%idxprom15.i152 = sext i32 %seg_offset.0.i151 to i64
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%arrayidx18.i154 = getelementptr inbounds i32, i32* null, i64 %idxprom15.i152
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%x1 = load i32, i32* %arrayidx18.i154, align 4
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br i1 undef, label %for.body51, label %for.body
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for.body51: ; preds = %is_sbox.exit155
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call fastcc void @get_switch_type(i32 %x1, i32 undef, i16 signext undef, i16 signext undef, i16* undef)
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unreachable
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}
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declare fastcc void @get_switch_type(i32, i32, i16 signext, i16 signext, i16* nocapture) nounwind ssp
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