mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
118 lines
3.4 KiB
LLVM
118 lines
3.4 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s
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;
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; Test folding of the sign-/zero-extend into the load instruction.
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;
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; Unscaled
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define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i8_to_i32
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; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: uxtb w0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i8 addrspace(256)*
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%3 = load i8, i8 addrspace(256)* %2
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%4 = zext i8 %3 to i32
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ret i32 %4
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}
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define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i16_to_i32
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; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: uxth w0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i16 addrspace(256)*
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%3 = load i16, i16 addrspace(256)* %2
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%4 = zext i16 %3 to i32
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ret i32 %4
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}
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define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i8_to_i64
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; CHECK: ldurb w[[REG:[0-9]+]], [x0, #-8]
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; CHECK: ubfx x0, x[[REG]], #0, #8
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i8 addrspace(256)*
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%3 = load i8, i8 addrspace(256)* %2
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%4 = zext i8 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i16_to_i64
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; CHECK: ldurh w[[REG:[0-9]+]], [x0, #-8]
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; CHECK: ubfx x0, x[[REG]], #0, #16
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i16 addrspace(256)*
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%3 = load i16, i16 addrspace(256)* %2
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%4 = zext i16 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i32_to_i64
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; CHECK: ldur w[[REG:[0-9]+]], [x0, #-8]
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; CHECK: ubfx x0, x[[REG]], #0, #32
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i32 addrspace(256)*
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%3 = load i32, i32 addrspace(256)* %2
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%4 = zext i32 %3 to i64
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ret i64 %4
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}
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define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i8_to_i32
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; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: sxtb w0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i8 addrspace(256)*
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%3 = load i8, i8 addrspace(256)* %2
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%4 = sext i8 %3 to i32
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ret i32 %4
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}
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define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i16_to_i32
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; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: sxth w0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i16 addrspace(256)*
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%3 = load i16, i16 addrspace(256)* %2
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%4 = sext i16 %3 to i32
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ret i32 %4
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}
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define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i8_to_i64
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; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: sxtb x0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i8 addrspace(256)*
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%3 = load i8, i8 addrspace(256)* %2
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%4 = sext i8 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i16_to_i64
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; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: sxth x0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i16 addrspace(256)*
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%3 = load i16, i16 addrspace(256)* %2
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%4 = sext i16 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i32_to_i64
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; CHECK: ldur [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: sxtw x0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i32 addrspace(256)*
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%3 = load i32, i32 addrspace(256)* %2
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%4 = sext i32 %3 to i64
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ret i64 %4
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}
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