Jack Carter bd71eea899 [Mips][msa] Added the simple builtins (madd_q to xori) ... Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188460 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-15 14:22:07 +00:00
..
AArch64	Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions	2013-08-15 08:26:11 +00:00
ARM	Let t2LDRBi8 and t2LDRBi12 have same Base Pointer	2013-08-14 16:35:29 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[Mips][msa] Added the simple builtins (madd_q to xori)	2013-08-15 14:22:07 +00:00
MSP430
NVPTX
PowerPC	Actually fix PPC64 64-bit GPR inline asm constraint matching	2013-08-14 20:05:04 +00:00
R600	R600/SI: Improve legalization of vector operations	2013-08-14 23:25:00 +00:00
SI
SPARC
SystemZ	[SystemZ] Use CLC and IPM to implement memcmp	2013-08-12 10:28:10 +00:00
Thumb
Thumb2
X86	Revert r188449 as it turns out we're just missing the instructions that need the v16i32/v16f32 matching.	2013-08-15 08:38:25 +00:00
XCore