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https://github.com/c64scene-ar/llvm-6502.git
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a99791886d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8
456 lines
19 KiB
C++
456 lines
19 KiB
C++
//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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#include "PPCRegisterInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/ADT/STLExtras.h"
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#include <cstdlib>
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#include <iostream>
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using namespace llvm;
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PPCRegisterInfo::PPCRegisterInfo()
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: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
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ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
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}
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void
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PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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if (SrcReg == PPC::LR) {
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// FIXME: this spills LR immediately to memory in one step. To do this, we
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// use R11, which we know cannot be used in the prolog/epilog. This is a
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// hack.
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BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
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} else if (RC == PPC::CRRCRegisterClass) {
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BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
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} else if (RC == PPC::GPRCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::G8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::F8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::F4RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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// Dest = LVX R0, R11
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
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BuildMI(MBB, MI, PPC::STVX, 3)
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.addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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}
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void
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PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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if (DestReg == PPC::LR) {
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
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BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
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} else if (RC == PPC::CRRCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
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BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
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} else if (RC == PPC::GPRCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
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} else if (RC == PPC::G8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
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} else if (RC == PPC::F8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
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} else if (RC == PPC::F4RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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// Dest = LVX R0, R11
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
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BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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}
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void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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if (RC == PPC::GPRCRegisterClass) {
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BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == PPC::G8RCRegisterClass) {
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BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == PPC::F4RCRegisterClass) {
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BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
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} else if (RC == PPC::F8RCRegisterClass) {
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BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
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} else if (RC == PPC::CRRCRegisterClass) {
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BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
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} else if (RC == PPC::VRRCRegisterClass) {
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BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else {
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std::cerr << "Attempt to copy register that is not GPR or FPR";
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abort();
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}
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}
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/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
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/// copy instructions, turning them into load/store instructions.
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MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
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unsigned OpNum,
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int FrameIndex) const {
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// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
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// it takes more than one instruction to store it.
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unsigned Opc = MI->getOpcode();
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if ((Opc == PPC::OR4 &&
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MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STW,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
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}
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} else if ((Opc == PPC::OR8 &&
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MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STD,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
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}
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} else if (Opc == PPC::FMRD) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STFD,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
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}
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} else if (Opc == PPC::FMRS) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STFS,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
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}
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}
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return 0;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(MachineFunction &MF) {
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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void PPCRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (hasFP(MF)) {
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// If we have a frame pointer, convert as follows:
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// ADJCALLSTACKDOWN -> addi, r1, r1, -amount
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// ADJCALLSTACKUP -> addi, r1, r1, amount
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MachineInstr *Old = I;
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unsigned Amount = Old->getOperand(0).getImmedValue();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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// Replace the pseudo instruction with a new instruction...
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if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
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BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount);
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} else {
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assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
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BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount);
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}
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}
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}
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MBB.erase(I);
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}
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void
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PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
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MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
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// Take into account whether it's an add or mem instruction
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unsigned OffIdx = (i == 2) ? 1 : 2;
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// Now add the frame object offset to the offset from r1.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(OffIdx).getImmedValue();
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// If we're not using a Frame Pointer that has been set to the value of the
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// SP before having the stack size subtracted from it, then add the stack size
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// to Offset to get the correct offset.
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Offset += MF.getFrameInfo()->getStackSize();
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if (Offset > 32767 || Offset < -32768) {
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// Insert a set of r0 with the full offset value before the ld, st, or add
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MachineBasicBlock *MBB = MI.getParent();
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BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16);
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BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
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// convert into indexed form of the instruction
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// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
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// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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assert(ImmToIdxMap.count(MI.getOpcode()) &&
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"No indexed form of load or store available!");
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unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
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MI.setOpcode(NewOpcode);
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MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
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MI.SetMachineOperandReg(2, PPC::R0);
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} else {
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switch (MI.getOpcode()) {
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case PPC::LWA:
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case PPC::LD:
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case PPC::STD:
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case PPC::STD_32:
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assert((Offset & 3) == 0 && "Invalid frame offset!");
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Offset >>= 2; // The actual encoded value has the low two bits zero.
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break;
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}
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MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
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Offset);
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}
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}
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// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
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// instruction selector. Based on the vector registers that have been used,
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// transform this into the appropriate ORI instruction.
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static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
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unsigned UsedRegMask = 0;
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#define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N)
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HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3);
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HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7);
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HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11);
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HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15);
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HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19);
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HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23);
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HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27);
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HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31);
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#undef HANDLEREG
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned DstReg = MI->getOperand(0).getReg();
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// If no registers are used, turn this into a copy.
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if (UsedRegMask == 0) {
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if (SrcReg != DstReg)
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BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg)
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.addReg(SrcReg).addReg(SrcReg);
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} else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
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BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
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.addReg(SrcReg).addImm(UsedRegMask);
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} else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
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BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
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.addReg(SrcReg).addImm(UsedRegMask >> 16);
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} else {
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BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
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.addReg(SrcReg).addImm(UsedRegMask >> 16);
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BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
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.addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
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}
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// Remove the old UPDATE_VRSAVE instruction.
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MI->getParent()->erase(MI);
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}
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void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Scan the first few instructions of the prolog, looking for an UPDATE_VRSAVE
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// instruction. If we find it, process it.
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for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
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if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
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HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
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break;
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}
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}
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// Move MBBI back to the beginning of the function.
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MBBI = MBB.begin();
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = MFI->getStackSize();
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// Get the alignments provided by the target, and the maximum alignment
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// (if any) of the fixed frame objects.
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unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
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unsigned MaxAlign = MFI->getMaxAlignment();
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// If we have calls, we cannot use the red zone to store callee save registers
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// and we must set up a stack frame, so calculate the necessary size here.
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if (MFI->hasCalls()) {
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// We reserve argument space for call sites in the function immediately on
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// entry to the current function. This eliminates the need for add/sub
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// brackets around call sites.
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NumBytes += MFI->getMaxCallFrameSize();
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}
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// If we are a leaf function, and use up to 224 bytes of stack space,
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// and don't have a frame pointer, then we do not need to adjust the stack
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// pointer (we fit in the Red Zone).
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if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls() &&
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MaxAlign <= TargetAlign)) {
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MFI->setStackSize(0);
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return;
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}
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// Add the size of R1 to NumBytes size for the store of R1 to the bottom
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// of the stack and round the size to a multiple of the alignment.
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unsigned Align = std::max(TargetAlign, MaxAlign);
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unsigned GPRSize = 4;
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unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
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NumBytes = (NumBytes+Size+Align-1)/Align*Align;
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// Update frame info to pretend that this is part of the stack...
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MFI->setStackSize(NumBytes);
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// Adjust stack pointer: r1 -= numbytes.
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if (NumBytes <= 32768) {
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BuildMI(MBB, MBBI, PPC::STWU, 3)
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.addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
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} else {
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int NegNumbytes = -NumBytes;
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BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
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BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
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.addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF);
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BuildMI(MBB, MBBI, PPC::STWUX, 3)
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.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
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}
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// If there is a preferred stack alignment, align R1 now
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// FIXME: If this ever matters, this could be made more efficient by folding
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// this into the code above, so that we don't issue two store+update
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// instructions.
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if (MaxAlign > TargetAlign) {
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assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
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BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
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.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
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BuildMI(MBB, MBBI, PPC::SUBFIC, 2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign);
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BuildMI(MBB, MBBI, PPC::STWUX, 3)
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.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
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}
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|
|
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// If there is a frame pointer, copy R1 (SP) into R31 (FP)
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if (hasFP(MF)) {
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BuildMI(MBB, MBBI, PPC::STW, 3)
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.addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
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BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
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}
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}
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|
|
|
void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const {
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
|
assert(MBBI->getOpcode() == PPC::BLR &&
|
|
"Can only insert epilog into returning blocks");
|
|
|
|
// Get the number of bytes allocated from the FrameInfo.
|
|
unsigned NumBytes = MF.getFrameInfo()->getStackSize();
|
|
unsigned GPRSize = 4;
|
|
|
|
if (NumBytes != 0) {
|
|
// If this function has a frame pointer, load the saved stack pointer from
|
|
// its stack slot.
|
|
if (hasFP(MF)) {
|
|
BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
|
|
.addSImm(GPRSize).addReg(PPC::R31);
|
|
}
|
|
|
|
// The loaded (or persistent) stack pointer value is offseted by the 'stwu'
|
|
// on entry to the function. Add this offset back now.
|
|
if (NumBytes < 32768) {
|
|
BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
|
|
.addReg(PPC::R1).addSImm(NumBytes);
|
|
} else {
|
|
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16);
|
|
BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
|
|
.addReg(PPC::R0).addImm(NumBytes & 0xFFFF);
|
|
BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1)
|
|
.addReg(PPC::R0).addReg(PPC::R1);
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
|
|
return getDwarfRegNum(hasFP(MF) ? PPC::R31 : PPC::R1);
|
|
}
|
|
|
|
#include "PPCGenRegisterInfo.inc"
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|
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