llvm-6502/test/CodeGen/X86/h-registers-0.ll
2010-04-28 08:30:49 +00:00

83 lines
1.7 KiB
LLVM

; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X86-64
; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X86-32
; Use h registers. On x86-64, codegen doesn't support general allocation
; of h registers yet, due to x86 encoding complications.
define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
; X86-64: bar64:
; X86-64: shrq $8, %rdi
; X86-64: incb %dil
; X86-32: bar64:
; X86-32: incb %ah
%t0 = lshr i64 %x, 8
%t1 = trunc i64 %t0 to i8
%t2 = add i8 %t1, 1
store i8 %t2, i8* %p
ret void
}
define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
; X86-64: bar32:
; X86-64: shrl $8, %edi
; X86-64: incb %dil
; X86-32: bar32:
; X86-32: incb %ah
%t0 = lshr i32 %x, 8
%t1 = trunc i32 %t0 to i8
%t2 = add i8 %t1, 1
store i8 %t2, i8* %p
ret void
}
define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
; X86-64: bar16:
; X86-64: shrl $8, %edi
; X86-64: incb %dil
; X86-32: bar16:
; X86-32: incb %ah
%t0 = lshr i16 %x, 8
%t1 = trunc i16 %t0 to i8
%t2 = add i8 %t1, 1
store i8 %t2, i8* %p
ret void
}
define i64 @qux64(i64 inreg %x) nounwind {
; X86-64: qux64:
; X86-64: movq %rdi, %rax
; X86-64: movzbl %ah, %eax
; X86-32: qux64:
; X86-32: movzbl %ah, %eax
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
ret i64 %t1
}
define i32 @qux32(i32 inreg %x) nounwind {
; X86-64: qux32:
; X86-64: movl %edi, %eax
; X86-64: movzbl %ah, %eax
; X86-32: qux32:
; X86-32: movzbl %ah, %eax
%t0 = lshr i32 %x, 8
%t1 = and i32 %t0, 255
ret i32 %t1
}
define i16 @qux16(i16 inreg %x) nounwind {
; X86-64: qux16:
; X86-64: movl %edi, %eax
; X86-64: movzbl %ah, %eax
; X86-32: qux16:
; X86-32: movzbl %ah, %eax
%t0 = lshr i16 %x, 8
ret i16 %t0
}