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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
292 lines
15 KiB
TableGen
292 lines
15 KiB
TableGen
//==- AArch64SchedA53.td - Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the ARM Cortex A53 processors.
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//
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//===----------------------------------------------------------------------===//
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// ===---------------------------------------------------------------------===//
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// The following definitions describe the simpler per-operand machine model.
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// This works with MachineScheduler. See MCSchedModel.h for details.
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// Cortex-A53 machine model for scheduling and other instruction cost heuristics.
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def CortexA53Model : SchedMachineModel {
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let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
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let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
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let LoadLatency = 3; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
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// Specification - Instruction Timings"
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// v 1.0 Spreadsheet
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}
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available.
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// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
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// Cortex-A53 is in-order.
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def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
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def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
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def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
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def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
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def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
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def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
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def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
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//===----------------------------------------------------------------------===//
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// Subtarget-specific SchedWrite types which both map the ProcResources and
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// set the latency.
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let SchedModel = CortexA53Model in {
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// ALU - Despite having a full latency of 4, most of the ALU instructions can
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// forward a cycle earlier and then two cycles earlier in the case of a
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// shift-only instruction. These latencies will be incorrect when the
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// result cannot be forwarded, but modeling isn't rocket surgery.
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def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
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def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
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def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
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def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
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def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
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def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
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// MAC
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def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
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def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
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// Div
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def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
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def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
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// Load
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def : WriteRes<WriteLD, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteLDIdx, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; }
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// Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd
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// below, choosing the median of 3 which makes the latency 6.
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// May model this more carefully in the future. The remaining
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// A53WriteVLD# types represent the 1-5 cycle issues explicitly.
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def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
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let ResourceCycles = [3]; }
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def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
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def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
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let ResourceCycles = [2]; }
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def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
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let ResourceCycles = [3]; }
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def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7;
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let ResourceCycles = [4]; }
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def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8;
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let ResourceCycles = [5]; }
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// Pre/Post Indexing - Performed as part of address generation which is already
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// accounted for in the WriteST* latencies below
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def : WriteRes<WriteAdr, []> { let Latency = 0; }
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// Store
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def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteSTP, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteSTIdx, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; }
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// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
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def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5;
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let ResourceCycles = [2];}
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def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
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def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
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let ResourceCycles = [2]; }
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def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
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let ResourceCycles = [3]; }
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// Branch
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def : WriteRes<WriteBr, [A53UnitB]>;
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def : WriteRes<WriteBrReg, [A53UnitB]>;
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def : WriteRes<WriteSys, [A53UnitB]>;
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def : WriteRes<WriteBarrier, [A53UnitB]>;
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def : WriteRes<WriteHint, [A53UnitB]>;
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// FP ALU
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def : WriteRes<WriteF, [A53UnitFPALU]> { let Latency = 6; }
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def : WriteRes<WriteFCmp, [A53UnitFPALU]> { let Latency = 6; }
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def : WriteRes<WriteFCvt, [A53UnitFPALU]> { let Latency = 6; }
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def : WriteRes<WriteFCopy, [A53UnitFPALU]> { let Latency = 6; }
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def : WriteRes<WriteFImm, [A53UnitFPALU]> { let Latency = 6; }
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def : WriteRes<WriteV, [A53UnitFPALU]> { let Latency = 6; }
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// FP Mul, Div, Sqrt
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def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; }
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def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33;
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let ResourceCycles = [29]; }
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def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; }
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def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18;
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let ResourceCycles = [14]; }
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def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
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let ResourceCycles = [29]; }
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def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17;
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let ResourceCycles = [13]; }
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def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
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let ResourceCycles = [28]; }
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//===----------------------------------------------------------------------===//
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// Subtarget-specific SchedRead types.
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// No forwarding for these reads.
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def : ReadAdvance<ReadExtrHi, 0>;
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def : ReadAdvance<ReadAdrBase, 0>;
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def : ReadAdvance<ReadVLD, 0>;
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// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
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// operands are needed one cycle later if and only if they are to be
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// shifted. Otherwise, they too are needed two cycle later. This same
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// ReadAdvance applies to Extended registers as well, even though there is
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// a seperate SchedPredicate for them.
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def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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def A53ReadISReg : SchedReadVariant<[
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SchedVar<RegShiftedPred, [A53ReadShifted]>,
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SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
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def : SchedAlias<ReadISReg, A53ReadISReg>;
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def A53ReadIEReg : SchedReadVariant<[
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SchedVar<RegExtendedPred, [A53ReadShifted]>,
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SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
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def : SchedAlias<ReadIEReg, A53ReadIEReg>;
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// MAC - Operands are generally needed one cycle later in the MAC pipe.
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// Accumulator operands are needed two cycles later.
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def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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// Div
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def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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//===----------------------------------------------------------------------===//
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// Subtarget-specific InstRWs.
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//---
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// Miscellaneous
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//---
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def : InstRW<[WriteI], (instrs COPY)>;
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//---
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// Vector Loads
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//---
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def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
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def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[A53WriteVLD3], (instregex "LD3Threev(2d)$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
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//---
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// Vector Stores
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//---
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def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
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//---
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// Floating Point MAC, DIV, SQRT
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//---
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def : InstRW<[A53WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>;
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def : InstRW<[A53WriteFMAC], (instregex "^FML(A|S).*")>;
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def : InstRW<[A53WriteFDivSP], (instrs FDIVSrr)>;
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def : InstRW<[A53WriteFDivDP], (instrs FDIVDrr)>;
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def : InstRW<[A53WriteFDivSP], (instregex "^FDIVv.*32$")>;
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def : InstRW<[A53WriteFDivDP], (instregex "^FDIVv.*64$")>;
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def : InstRW<[A53WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
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def : InstRW<[A53WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
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}
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