Asiri Rathnayake 61f3193001 Fix yet another unseen regression caused by r223113 ... r223113 added support for ARM modified immediate assembly syntax. Which assumes all immediate operands are prefixed with a '#'. This assumption is wrong as per the ARMARM - which recommends that all '#' characters be treated optional. The current patch fixes this regression and adds a test case. A follow-up patch will expand the test coverage to other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223381 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-04 19:34:59 +00:00
..
AArch64
ARM	Fix yet another unseen regression caused by r223113	2014-12-04 19:34:59 +00:00
AsmParser
COFF
Disassembler	[Hexagon] Adding lit exception if Hexagon isn't built.	2014-12-04 04:28:38 +00:00
ELF	Commit back the correct bits of r222760 (was r222538).	2014-11-27 17:13:56 +00:00
Hexagon
MachO
Markup
Mips	The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.	2014-12-01 11:12:04 +00:00
PowerPC	[PowerPC] Add asm support for cache-inhibited ld/st instructions	2014-11-30 10:15:56 +00:00
R600
Sparc
SystemZ
X86	[X86][MC] Intel syntax: accept implicit memory operand sizes larger than 80.	2014-12-03 02:03:26 +00:00