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for all the processors where I have tried it, and even when it might not help performance, the cost is quite low. The opportunities for duplicating indirect branches are limited by other factors so code size does not change much due to tail duplicating indirect branches aggressively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
178 lines
5.5 KiB
C++
178 lines
5.5 KiB
C++
//===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARM specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMSubtarget.h"
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#include "ARMGenSubtarget.inc"
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#include "llvm/GlobalValue.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/SmallVector.h"
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using namespace llvm;
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static cl::opt<bool>
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ReserveR9("arm-reserve-r9", cl::Hidden,
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cl::desc("Reserve R9, making it unavailable as GPR"));
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static cl::opt<bool>
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UseNEONFP("arm-use-neon-fp",
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cl::desc("Use NEON for single-precision FP"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool>
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UseMOVT("arm-use-movt",
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cl::init(true), cl::Hidden);
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ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
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bool isT)
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: ARMArchVersion(V4T)
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, ARMFPUType(None)
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, UseNEONForSinglePrecisionFP(UseNEONFP)
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, IsThumb(isT)
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, ThumbMode(Thumb1)
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, PostRAScheduler(false)
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, IsR9Reserved(ReserveR9)
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, UseMovt(UseMOVT)
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, stackAlignment(4)
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, CPUString("generic")
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, TargetType(isELF) // Default to ELF unless otherwise specified.
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, TargetABI(ARM_ABI_APCS) {
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// default to soft float ABI
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if (FloatABIType == FloatABI::Default)
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FloatABIType = FloatABI::Soft;
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// Determine default and user specified characteristics
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// Parse features string.
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CPUString = ParseSubtargetFeatures(FS, CPUString);
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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unsigned Len = TT.length();
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unsigned Idx = 0;
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if (Len >= 5 && TT.substr(0, 4) == "armv")
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Idx = 4;
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else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
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IsThumb = true;
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if (Len >= 7 && TT[5] == 'v')
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Idx = 6;
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}
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if (Idx) {
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unsigned SubVer = TT[Idx];
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if (SubVer > '4' && SubVer <= '9') {
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if (SubVer >= '7') {
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ARMArchVersion = V7A;
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} else if (SubVer == '6') {
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ARMArchVersion = V6;
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
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ARMArchVersion = V6T2;
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} else if (SubVer == '5') {
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ARMArchVersion = V5T;
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
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ARMArchVersion = V5TE;
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}
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if (ARMArchVersion >= V6T2)
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ThumbMode = Thumb2;
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}
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}
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// Thumb2 implies at least V6T2.
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if (ARMArchVersion < V6T2 && ThumbMode >= Thumb2)
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ARMArchVersion = V6T2;
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if (Len >= 10) {
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if (TT.find("-darwin") != std::string::npos)
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// arm-darwin
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TargetType = isDarwin;
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}
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if (TT.find("eabi") != std::string::npos)
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TargetABI = ARM_ABI_AAPCS;
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if (isAAPCS_ABI())
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stackAlignment = 8;
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if (isTargetDarwin())
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IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
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if (!isThumb() || hasThumb2())
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PostRAScheduler = true;
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// Set CPU specific features.
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if (CPUString == "cortex-a8") {
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// On Cortex-a8, it's faster to perform some single-precision FP
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// operations with NEON instructions.
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if (UseNEONFP.getPosition() == 0)
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UseNEONForSinglePrecisionFP = true;
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}
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}
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/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
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bool
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ARMSubtarget::GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) const {
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if (RelocM == Reloc::Static)
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return false;
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// GV with ghost linkage (in JIT lazy compilation mode) do not require an
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// extra load from stub.
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bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
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if (!isTargetDarwin()) {
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// Extra load is needed for all externally visible.
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if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
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return false;
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return true;
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} else {
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if (RelocM == Reloc::PIC_) {
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return false;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return true;
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// If symbol visibility is hidden, we have a stub for common symbol
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// references and external declarations.
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if (isDecl || GV->hasCommonLinkage())
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// Hidden $non_lazy_ptr reference.
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return true;
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return false;
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} else {
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return false;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return true;
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}
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}
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return false;
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}
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bool ARMSubtarget::enablePostRAScheduler(
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CodeGenOpt::Level OptLevel,
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TargetSubtarget::AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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Mode = TargetSubtarget::ANTIDEP_CRITICAL;
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(&ARM::GPRRegClass);
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return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
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}
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