mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f19c6f5763
eliminateFrameIndex() has been reworked to handle both small & large frames with either a FP or SP. An additional Slot is required for Scavenging spills when not using FP for large frames. Reworked the handling of Register Scavenging. Whether we are using an FP or not, whether it is a large frame or not, and whether we are using a large code model or not are now independent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196091 91177308-0d34-0410-b5e6-96231b3b80d8
235 lines
6.7 KiB
LLVM
235 lines
6.7 KiB
LLVM
; RUN: llc < %s -march=xcore | FileCheck %s
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; RUN: llc < %s -march=xcore -disable-fp-elim | FileCheck %s -check-prefix=CHECKFP
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; When using SP for small frames, we don't need any scratch registers (SR).
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; When using SP for large frames, we may need two scratch registers.
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; When using FP, for large or small frames, we may need one scratch register.
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; FP + small frame: spill FP+SR = entsp 2
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; CHECKFP-LABEL: f1
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; CHECKFP: entsp 2
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: retsp 2
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;
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; !FP + small frame: no spills = no stack adjustment needed
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; CHECK-LABEL: f1
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; CHECK: stw lr, sp[0]
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; CHECK: ldw lr, sp[0]
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; CHECK-NEXT: retsp 0
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define void @f1() nounwind {
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entry:
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tail call void asm sideeffect "", "~{lr}"() nounwind
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ret void
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}
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; FP + small frame: spill FP+SR+R0+LR = entsp 3 + extsp 1
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; CHECKFP-LABEL:f3
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; CHECKFP: entsp 3
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[2]
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; CHECKFP-NEXT: mov [[REG]], r0
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: bl f2
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: mov r0, [[REG]]
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; CHECKFP-NEXT: ldw [[REG]], r10[2]
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; CHECKFP-NEXT: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: retsp 3
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;
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; !FP + small frame: spill R0+LR = entsp 2
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; CHECK-LABEL: f3
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; CHECK: entsp 2
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; CHECK-NEXT: stw [[REG:r[4-9]+]], sp[1]
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; CHECK-NEXT: mov [[REG]], r0
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; CHECK-NEXT: bl f2
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; CHECK-NEXT: mov r0, [[REG]]
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; CHECK-NEXT: ldw [[REG]], sp[1]
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; CHECK-NEXT: retsp 2
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declare void @f2()
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define i32 @f3(i32 %i) nounwind {
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entry:
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call void @f2()
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ret i32 %i
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}
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; FP + large frame: spill FP+SR = entsp 2 + 100000
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; CHECKFP-LABEL: f4
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; CHECKFP: extsp 65535
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
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; CHECKFP-NEXT: extsp 34467
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 400008
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_offset 10, -400004
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_register 10
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; CHECKFP-NEXT: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: ldaw sp, sp[65535]
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; CHECKFP-NEXT: ldaw sp, sp[34467]
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; CHECKFP-NEXT: retsp 0
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;
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; !FP + large frame: spill SR+SR = entsp 2 + 100000
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; CHECK-LABEL: f4
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; CHECK: extsp 65535
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 262140
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; CHECK-NEXT: extsp 34467
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 400008
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; CHECK-NEXT: ldaw sp, sp[65535]
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; CHECK-NEXT: ldaw sp, sp[34467]
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; CHECK-NEXT: retsp 0
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define void @f4() {
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entry:
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%0 = alloca [100000 x i32]
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ret void
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}
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; FP + large frame: spill FP+SR+R4+LR = entsp 3 + 200000 + extsp 1
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; CHECKFP: .section .cp.rodata.cst4,"aMc",@progbits,4
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; CHECKFP-NEXT: .align 4
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; CHECKFP-NEXT: .LCPI[[CNST0:[0-9_]+]]:
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; CHECKFP-NEXT: .long 200002
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; CHECKFP-NEXT: .LCPI[[CNST1:[0-9_]+]]:
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; CHECKFP-NEXT: .long 200001
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; CHECKFP-NEXT: .text
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; CHECKFP-LABEL: f6
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; CHECKFP: entsp 65535
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_offset 15, 0
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; CHECKFP-NEXT: extsp 65535
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 524280
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; CHECKFP-NEXT: extsp 65535
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 786420
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; CHECKFP-NEXT: extsp 3398
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 800012
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_offset 10, -800008
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_register 10
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; CHECKFP-NEXT: ldw r1, cp[.LCPI[[CNST0]]]
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; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[r1]
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_offset 4, -4
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; CHECKFP-NEXT: mov [[REG]], r0
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: ldaw r0, r10[2]
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; CHECKFP-NEXT: bl f5
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: ldw r1, cp[.LCPI3_1]
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; CHECKFP-NEXT: ldaw r0, r10[r1]
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: bl f5
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: mov r0, [[REG]]
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; CHECKFP-NEXT: ldw r1, cp[.LCPI[[CNST0]]]
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; CHECKFP-NEXT: ldw [[REG]], r10[r1]
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; CHECKFP-NEXT: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: ldaw sp, sp[65535]
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; CHECKFP-NEXT: ldaw sp, sp[65535]
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; CHECKFP-NEXT: ldaw sp, sp[65535]
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; CHECKFP-NEXT: retsp 3398
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;
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; !FP + large frame: spill SR+SR+R4+LR = entsp 4 + 200000
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; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
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; CHECK-NEXT: .align 4
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; CHECK-NEXT: .LCPI[[CNST0:[0-9_]+]]:
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; CHECK-NEXT: .long 200003
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; CHECK-NEXT: .LCPI[[CNST1:[0-9_]+]]:
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; CHECK-NEXT: .long 200002
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; CHECK-NEXT: .text
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; CHECK-LABEL: f6
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; CHECK: entsp 65535
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 262140
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_offset 15, 0
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; CHECK-NEXT: extsp 65535
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 524280
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; CHECK-NEXT: extsp 65535
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 786420
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; CHECK-NEXT: extsp 3399
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 800016
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; CHECK-NEXT: ldaw r1, sp[0]
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; CHECK-NEXT: ldw r2, cp[.LCPI[[CNST0]]]
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; CHECK-NEXT: stw [[REG:r[4-9]+]], r1[r2]
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_offset 4, -4
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; CHECK-NEXT: mov [[REG]], r0
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; CHECK-NEXT: ldaw r0, sp[3]
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; CHECK-NEXT: bl f5
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; CHECK-NEXT: ldaw r0, sp[0]
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; CHECK-NEXT: ldw r1, cp[.LCPI[[CNST1]]]
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; CHECK-NEXT: ldaw r0, r0[r1]
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; CHECK-NEXT: bl f5
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; CHECK-NEXT: mov r0, [[REG]]
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; CHECK-NEXT: ldaw [[REG]], sp[0]
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; CHECK-NEXT: ldw r1, cp[.LCPI[[CNST0]]]
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; CHECK-NEXT: ldw [[REG]], [[REG]][r1]
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; CHECK-NEXT: ldaw sp, sp[65535]
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; CHECK-NEXT: ldaw sp, sp[65535]
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; CHECK-NEXT: ldaw sp, sp[65535]
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; CHECK-NEXT: retsp 3399
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declare void @f5(i32*)
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define i32 @f6(i32 %i) {
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entry:
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%0 = alloca [200000 x i32]
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%1 = getelementptr inbounds [200000 x i32]* %0, i32 0, i32 0
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call void @f5(i32* %1)
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%2 = getelementptr inbounds [200000 x i32]* %0, i32 0, i32 199999
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call void @f5(i32* %2)
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ret i32 %i
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}
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; FP + large frame: spill FP+SR+LR = entsp 2 + 32768 + extsp 1
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; CHECKFP-LABEL:f8
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; CHECKFP: entsp 32770
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: mkmsk r1, 15
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; CHECKFP-NEXT: ldaw r0, r10[r1]
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: bl f5
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: retsp 32770
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;
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; !FP + large frame: spill SR+SR+LR = entsp 3 + 32768
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; CHECK-LABEL:f8
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; CHECK: entsp 32771
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; CHECK-NEXT: ldaw r0, sp[32768]
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; CHECK-NEXT: bl f5
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; CHECK-NEXT: retsp 32771
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define void @f8() nounwind {
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entry:
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%0 = alloca [32768 x i32]
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%1 = getelementptr inbounds [32768 x i32]* %0, i32 0, i32 32765
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call void @f5(i32* %1)
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ret void
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}
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