mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Summary: I don't know why every singled backend had to redeclare its own DataLayout. There was a virtual getDataLayout() on the common base TargetMachine, the default implementation returned nullptr. It was not clear from this that we could assume at call site that a DataLayout will be available with each Target. Now getDataLayout() is no longer virtual and return a pointer to the DataLayout member of the common base TargetMachine. I plan to turn it into a reference in a future patch. The only backend that didn't have a DataLayout previsouly was the CPPBackend. It now initializes the default DataLayout. This commit is NFC for all the other backends. Test Plan: clang+llvm ninja check-all Reviewers: echristo Subscribers: jfb, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8243 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231987 91177308-0d34-0410-b5e6-96231b3b80d8
130 lines
4.3 KiB
C++
130 lines
4.3 KiB
C++
//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file declares the ARM specific subclass of TargetMachine.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
|
|
#define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
|
|
|
|
#include "ARMInstrInfo.h"
|
|
#include "ARMSubtarget.h"
|
|
#include "llvm/IR/DataLayout.h"
|
|
#include "llvm/Target/TargetMachine.h"
|
|
|
|
namespace llvm {
|
|
|
|
class ARMBaseTargetMachine : public LLVMTargetMachine {
|
|
public:
|
|
enum ARMABI {
|
|
ARM_ABI_UNKNOWN,
|
|
ARM_ABI_APCS,
|
|
ARM_ABI_AAPCS // ARM EABI
|
|
} TargetABI;
|
|
|
|
protected:
|
|
std::unique_ptr<TargetLoweringObjectFile> TLOF;
|
|
ARMSubtarget Subtarget;
|
|
bool isLittle;
|
|
mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
|
|
|
|
public:
|
|
ARMBaseTargetMachine(const Target &T, StringRef TT,
|
|
StringRef CPU, StringRef FS,
|
|
const TargetOptions &Options,
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
CodeGenOpt::Level OL,
|
|
bool isLittle);
|
|
~ARMBaseTargetMachine() override;
|
|
|
|
const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
|
|
const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
|
|
bool isLittleEndian() const { return isLittle; }
|
|
|
|
/// \brief Get the TargetIRAnalysis for this target.
|
|
TargetIRAnalysis getTargetIRAnalysis() override;
|
|
|
|
// Pass Pipeline Configuration
|
|
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
|
|
|
|
TargetLoweringObjectFile *getObjFileLowering() const override {
|
|
return TLOF.get();
|
|
}
|
|
};
|
|
|
|
/// ARMTargetMachine - ARM target machine.
|
|
///
|
|
class ARMTargetMachine : public ARMBaseTargetMachine {
|
|
virtual void anchor();
|
|
public:
|
|
ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
|
|
const TargetOptions &Options, Reloc::Model RM,
|
|
CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
|
|
};
|
|
|
|
/// ARMLETargetMachine - ARM little endian target machine.
|
|
///
|
|
class ARMLETargetMachine : public ARMTargetMachine {
|
|
void anchor() override;
|
|
public:
|
|
ARMLETargetMachine(const Target &T, StringRef TT,
|
|
StringRef CPU, StringRef FS, const TargetOptions &Options,
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
CodeGenOpt::Level OL);
|
|
};
|
|
|
|
/// ARMBETargetMachine - ARM big endian target machine.
|
|
///
|
|
class ARMBETargetMachine : public ARMTargetMachine {
|
|
void anchor() override;
|
|
public:
|
|
ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
|
|
const TargetOptions &Options, Reloc::Model RM,
|
|
CodeModel::Model CM, CodeGenOpt::Level OL);
|
|
};
|
|
|
|
/// ThumbTargetMachine - Thumb target machine.
|
|
/// Due to the way architectures are handled, this represents both
|
|
/// Thumb-1 and Thumb-2.
|
|
///
|
|
class ThumbTargetMachine : public ARMBaseTargetMachine {
|
|
virtual void anchor();
|
|
public:
|
|
ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
|
|
const TargetOptions &Options, Reloc::Model RM,
|
|
CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
|
|
};
|
|
|
|
/// ThumbLETargetMachine - Thumb little endian target machine.
|
|
///
|
|
class ThumbLETargetMachine : public ThumbTargetMachine {
|
|
void anchor() override;
|
|
public:
|
|
ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
|
|
StringRef FS, const TargetOptions &Options,
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
CodeGenOpt::Level OL);
|
|
};
|
|
|
|
/// ThumbBETargetMachine - Thumb big endian target machine.
|
|
///
|
|
class ThumbBETargetMachine : public ThumbTargetMachine {
|
|
void anchor() override;
|
|
public:
|
|
ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
|
|
StringRef FS, const TargetOptions &Options,
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
CodeGenOpt::Level OL);
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|