mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 16:30:00 +00:00
7836fc129a
Every function has the address of its frame in the beginning of code section. The frame address is retrieved and used to pass arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68597 91177308-0d34-0410-b5e6-96231b3b80d8
34 lines
1.1 KiB
TableGen
34 lines
1.1 KiB
TableGen
//===- PIC16RegisterInfo.td - PIC16 Register defs ------------*- tblgen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Declarations that describe the PIC16 register file
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class PIC16Reg<string n> : Register<n> {
|
|
let Namespace = "PIC16";
|
|
}
|
|
|
|
// PIC16 Registers.
|
|
def W : PIC16Reg<"W">;
|
|
def FSR0 : PIC16Reg<"FSR0">;
|
|
def FSR1 : PIC16Reg<"FSR1">;
|
|
def BS : PIC16Reg<"BS">;
|
|
def PCLATH : PIC16Reg<"PCLATH">;
|
|
|
|
def STATUS : PIC16Reg<"STATUS">;
|
|
|
|
// PIC16 Register classes.
|
|
def GPR : RegisterClass<"PIC16", [i8], 8, [W]>;
|
|
def FSR16 : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]>;
|
|
def BSR : RegisterClass<"PIC16", [i8], 8, [BS]>;
|
|
def PCLATHR : RegisterClass<"PIC16", [i8], 8, [PCLATH]>;
|
|
def STATUSR : RegisterClass<"PIC16", [i8], 8, [STATUS]>;
|
|
|