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http://reviews.llvm.org/D10474 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241150 91177308-0d34-0410-b5e6-96231b3b80d8
290 lines
5.8 KiB
TableGen
290 lines
5.8 KiB
TableGen
//=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes microMIPS32r6 instruction formats.
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//
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//===----------------------------------------------------------------------===//
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class MMR6Arch<string opstr> {
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string Arch = "micromipsr6";
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string BaseOpcode = opstr;
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}
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class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rd;
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let Inst{15-12} = 0b0000;
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let Inst{11-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
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bits<21> addr;
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bits<5> hint;
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bits<32> Inst;
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let Inst{31-26} = opgroup;
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let Inst{25-21} = hint;
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let Inst{20-16} = addr{20-16};
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let Inst{15-12} = funct;
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let Inst{11-0} = addr{11-0};
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}
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class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
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bits<5> rd;
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bits<5> rt;
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10} = 0;
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let Inst{9-0} = funct;
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}
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class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
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bits<5> rt;
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bits<5> rs;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-0} = imm16;
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}
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class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
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: MMR6Arch<instr_asm> {
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bits<5> rd;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rd;
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let Inst{20-16} = rt;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
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bits<5> rt;
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bits<19> imm;
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bits<32> Inst;
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let Inst{31-26} = 0b011110;
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let Inst{25-21} = rt;
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let Inst{20-19} = funct;
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let Inst{18-0} = imm;
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}
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class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = 0b011110;
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let Inst{25-21} = rt;
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let Inst{20-16} = funct;
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let Inst{15-0} = imm;
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}
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class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10} = 0;
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let Inst{9-0} = funct;
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}
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class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0b00000;
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let Inst{15-11} = rt;
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let Inst{10-6} = 0b00001;
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let Inst{5-0} = funct;
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}
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class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<2> bp;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-9} = bp;
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let Inst{8-6} = 0b000;
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let Inst{5-0} = funct;
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}
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class AUI_FM_MMR6 : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = 0b000100;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-0} = imm;
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}
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class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<2> imm2;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10-9} = imm2;
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let Inst{8-6} = 0b000;
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let Inst{5-0} = funct;
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}
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class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = rt;
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let Inst{20-16} = 0b00000;
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let Inst{15-0} = offset;
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}
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class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = rt;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
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bits<32> Inst;
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let Inst{31-26} = 0x00;
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let Inst{25-16} = 0x00;
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let Inst{15-6} = 0x3cd;
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let Inst{5-0} = 0x3c;
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}
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class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
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bits<32> Inst;
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let Inst{31-26} = 0x00;
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let Inst{25-17} = 0x00;
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let Inst{16-16} = 0x01;
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let Inst{15-6} = 0x3cd;
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let Inst{5-0} = 0x3c;
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}
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class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
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bits<10> code_1;
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bits<10> code_2;
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bits<32> Inst;
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let Inst{31-26} = 0x0;
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let Inst{25-16} = code_1;
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let Inst{15-6} = code_2;
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let Inst{5-0} = 0x07;
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}
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class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
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bits<32> Inst;
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let Inst{31-26} = 0x0;
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let Inst{25-21} = 0x0;
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let Inst{20-16} = 0x0;
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let Inst{15-11} = op;
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let Inst{10-6} = 0x0;
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let Inst{5-0} = 0x0;
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}
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class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
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bits<32> Inst;
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bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
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let Inst{31-26} = 0x00;
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let Inst{25-21} = 0x00;
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let Inst{20-16} = rt;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0x3c;
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}
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class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
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bits<5> rd;
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bits<5> rt;
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bits<5> shamt;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rd;
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let Inst{20-16} = rt;
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let Inst{15-11} = shamt;
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let Inst{10} = rotate;
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let Inst{9-0} = funct;
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}
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