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4784f1fc73
llvm-6502/test/CodeGen
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Evan Cheng 4784f1fc73 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. 
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 08:49:04 +00:00
..
Alpha
ARM Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. 2009-06-30 08:49:04 +00:00
CBackend Fix an erroneous check for isFNeg; the FNeg case is handled 2009-06-04 23:43:29 +00:00
CellSPU Add some generic expansion logic for SMULO and UMULO. Fixes UMULO 2009-06-16 06:58:29 +00:00
CPP Fix code emission for conditional branches. 2009-05-04 19:10:38 +00:00
Generic Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
IA64
Mips Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
MSP430 Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
PowerPC Don't grep the -debug output. This isn't the way to test changes. 2009-06-25 21:59:32 +00:00
SPARC Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
Thumb We should run these tests as well. 2009-06-24 21:36:26 +00:00
Thumb2 A few more load instructions. 2009-06-30 02:15:48 +00:00
X86 FIX PR 4459. 2009-06-29 20:29:59 +00:00
XCore Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00