Colin LeMahieu ec51bc6f3a [Hexagon] Adding sub/and/or reg, imm forms ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223522 91177308-0d34-0410-b5e6-96231b3b80d8

2014-12-05 21:38:29 +00:00

..

AArch64

Update AArch64 ELF relocations to ABI 1.0

2014-11-26 10:49:18 +00:00

ARM

Improvements to ARM assembler tests

2014-12-05 16:33:56 +00:00

AsmParser

MC: AsmLexer: handle multi-character CommentStrings correctly

2014-08-14 02:51:43 +00:00

COFF

MC, COFF: Use relocations for function references inside the section

2014-11-11 08:43:57 +00:00

Disassembler

[Hexagon] Adding sub/and/or reg, imm forms

2014-12-05 21:38:29 +00:00

ELF

Commit back the correct bits of r222760 (was r222538).

2014-11-27 17:13:56 +00:00

Hexagon

[Hexagon] Adding cmp* immediate form instructions.

2014-11-26 19:43:12 +00:00

MachO

Don't produce relocations for a difference in a section with no symbols.

2014-11-04 22:10:33 +00:00

Markup

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Mips

The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.

2014-12-01 11:12:04 +00:00

PowerPC

[PowerPC] Add asm support for cache-inhibited ld/st instructions

2014-11-30 10:15:56 +00:00

R600

R600/SI: Start implementing an assembler

2014-11-14 14:08:00 +00:00

Sparc

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00

SystemZ

Exclude known and bugzilled failures from UBSan bootstrap

2014-09-17 20:17:52 +00:00

X86

[X86][MC] Intel syntax: accept implicit memory operand sizes larger than 80.

2014-12-03 02:03:26 +00:00