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https://github.com/c64scene-ar/llvm-6502.git
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47b92f3d83
"With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144414 91177308-0d34-0410-b5e6-96231b3b80d8
233 lines
7.4 KiB
C++
233 lines
7.4 KiB
C++
//===-- MipsASMBackend.cpp - ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "MipsFixupKinds.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Object/MachOFormat.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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// Add/subtract and shift
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switch (Kind) {
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default:
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break;
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case Mips::fixup_Mips_PC16:
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// So far we are only using this type for branches.
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// For branches we start 1 instruction after the branch
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// so the displacement will be one instruction size less.
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Value -= 4;
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// The displacement is then divided by 4 to give us an 18 bit
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// address range.
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Value >>= 2;
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break;
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case Mips::fixup_Mips_26:
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// So far we are only using this type for jumps.
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// The displacement is then divided by 4 to give us an 28 bit
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// address range.
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Value >>= 2;
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break;
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}
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// Mask off value for placement as an operand
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switch (Kind) {
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default:
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break;
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case FK_Data_4:
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Value &= 0xffffffff;
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break;
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case Mips::fixup_Mips_26:
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Value &= 0x03ffffff;
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break;
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case Mips::fixup_Mips_LO16:
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case Mips::fixup_Mips_PC16:
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Value &= 0x0000ffff;
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break;
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}
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return Value;
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}
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namespace {
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class MipsELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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MipsELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
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bool HasRelocationAddend)
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: MCELFObjectTargetWriter(is64Bit, OSType, EMachine,
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HasRelocationAddend) {}
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};
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class MipsAsmBackend : public MCAsmBackend {
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public:
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MipsAsmBackend(const Target &T) : MCAsmBackend() {}
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/// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
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/// data fragment, at the offset specified by the fixup and following the
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/// fixup kind as appropriate.
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void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const {
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unsigned Kind = (unsigned)Fixup.getKind();
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Value = adjustFixupValue(Kind, Value);
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if (!Value)
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return; // Doesn't change encoding.
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unsigned Offset = Fixup.getOffset();
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case Mips::fixup_Mips_GOT16: // This will be fixed up at link time
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break;
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case FK_Data_4:
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case Mips::fixup_Mips_26:
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case Mips::fixup_Mips_LO16:
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case Mips::fixup_Mips_PC16:
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// For each byte of the fragment that the fixup touches, mask i
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// the fixup value. The Value has been "split up" into the appr
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// bitfields above.
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for (unsigned i = 0; i != 4; ++i) // FIXME - Need to support 2 and 8 bytes
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Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
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break;
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}
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}
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unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
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// This table *must* be in the order that the fixup_* kinds a
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// MipsFixupKinds.h.
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//
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// name offset bits flags
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{ "fixup_Mips_NONE", 0, 0, 0 },
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{ "fixup_Mips_16", 0, 16, 0 },
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{ "fixup_Mips_32", 0, 32, 0 },
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{ "fixup_Mips_REL32", 0, 32, 0 },
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{ "fixup_Mips_26", 0, 26, 0 },
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{ "fixup_Mips_HI16", 0, 16, 0 },
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{ "fixup_Mips_LO16", 0, 16, 0 },
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{ "fixup_Mips_GPREL16", 0, 16, 0 },
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{ "fixup_Mips_LITERAL", 0, 16, 0 },
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{ "fixup_Mips_GOT16", 0, 16, 0 },
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{ "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_CALL16", 0, 16, 0 },
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{ "fixup_Mips_GPREL32", 0, 32, 0 },
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{ "fixup_Mips_SHIFT5", 6, 5, 0 },
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{ "fixup_Mips_SHIFT6", 6, 5, 0 },
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{ "fixup_Mips_64", 0, 64, 0 },
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{ "fixup_Mips_TLSGD", 0, 16, 0 },
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{ "fixup_Mips_GOTTPREL", 0, 16, 0 },
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{ "fixup_Mips_TPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_TPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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/// @name Target Relaxation Interfaces
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/// @{
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/// MayNeedRelaxation - Check whether the given instruction may need
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/// relaxation.
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///
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/// \param Inst - The instruction to test.
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bool MayNeedRelaxation(const MCInst &Inst) const {
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return false;
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}
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/// RelaxInstruction - Relax the instruction in the given fragment
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/// to the next wider instruction.
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///
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/// \param Inst - The instruction to relax, which may be the same
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/// as the output.
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/// \parm Res [output] - On return, the relaxed instruction.
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void RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
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}
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/// @}
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/// WriteNopData - Write an (optimal) nop sequence of Count bytes
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/// to the given output. If the target cannot generate such a sequence,
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/// it should return an error.
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///
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/// \return - True on success.
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bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
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return true;
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}
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};
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class MipsEB_AsmBackend : public MipsAsmBackend {
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public:
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Triple::OSType OSType;
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MipsEB_AsmBackend(const Target &T, Triple::OSType _OSType)
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: MipsAsmBackend(T), OSType(_OSType) {}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createELFObjectWriter(createELFObjectTargetWriter(),
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OS, /*IsLittleEndian*/ false);
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}
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MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
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return new MipsELFObjectWriter(false, OSType, ELF::EM_MIPS, false);
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}
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};
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class MipsEL_AsmBackend : public MipsAsmBackend {
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public:
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Triple::OSType OSType;
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MipsEL_AsmBackend(const Target &T, Triple::OSType _OSType)
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: MipsAsmBackend(T), OSType(_OSType) {}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createELFObjectWriter(createELFObjectTargetWriter(),
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OS, /*IsLittleEndian*/ true);
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}
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MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
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return new MipsELFObjectWriter(false, OSType, ELF::EM_MIPS, false);
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}
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};
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} // namespace
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MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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// just return little endian for now
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//
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return new MipsEL_AsmBackend(T, Triple(TT).getOS());
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}
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