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* Fix initialization order problems... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@762 91177308-0d34-0410-b5e6-96231b3b80d8
935 lines
28 KiB
C++
935 lines
28 KiB
C++
// $Id$
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//***************************************************************************
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// File:
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// SchedGraph.cpp
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//
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// Purpose:
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// Scheduling graph based on SSA graph plus extra dependence edges
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// capturing dependences due to machine resources (machine registers,
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// CC registers, and any others).
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//
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// History:
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// 7/20/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "SchedGraph.h"
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#include "llvm/InstrTypes.h"
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#include "llvm/Instruction.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/Method.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Target/MachineRegInfo.h"
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#include "llvm/Support/StringExtras.h"
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#include "llvm/iOther.h"
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#include <algorithm>
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//*********************** Internal Data Structures *************************/
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typedef vector< pair<SchedGraphNode*, unsigned int> > RefVec;
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// The following needs to be a class, not a typedef, so we can use
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// an opaque declaration in SchedGraph.h
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struct RegToRefVecMap: public hash_map<int, RefVec> {
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typedef hash_map<int, RefVec>:: iterator iterator;
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typedef hash_map<int, RefVec>::const_iterator const_iterator;
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};
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//
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// class SchedGraphEdge
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//
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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SchedGraphEdgeDepType _depType,
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DataDepOrderType _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(_depType),
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depOrderType(_depOrderType),
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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val(NULL)
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{
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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const Value* _val,
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DataDepOrderType _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(DefUseDep),
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depOrderType(_depOrderType),
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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val(_val)
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{
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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unsigned int _regNum,
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DataDepOrderType _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(MachineRegister),
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depOrderType(_depOrderType),
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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machineRegNum(_regNum)
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{
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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ResourceId _resourceId,
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(MachineResource),
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depOrderType(NonDataDep),
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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resourceId(_resourceId)
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{
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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/*dtor*/
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SchedGraphEdge::~SchedGraphEdge()
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{
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}
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void SchedGraphEdge::dump(int indent=0) const {
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printIndent(indent); cout << *this;
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}
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//
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// class SchedGraphNode
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//
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/*ctor*/
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SchedGraphNode::SchedGraphNode(unsigned int _nodeId,
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const Instruction* _instr,
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const MachineInstr* _minstr,
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const TargetMachine& target)
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: nodeId(_nodeId),
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instr(_instr),
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minstr(_minstr),
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latency(0)
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{
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if (minstr)
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{
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MachineOpCode mopCode = minstr->getOpCode();
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latency = target.getInstrInfo().hasResultInterlock(mopCode)
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? target.getInstrInfo().minLatency(mopCode)
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: target.getInstrInfo().maxLatency(mopCode);
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}
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}
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/*dtor*/
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SchedGraphNode::~SchedGraphNode()
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{
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}
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void SchedGraphNode::dump(int indent=0) const {
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printIndent(indent); cout << *this;
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}
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inline void
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SchedGraphNode::addInEdge(SchedGraphEdge* edge)
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{
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inEdges.push_back(edge);
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}
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inline void
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SchedGraphNode::addOutEdge(SchedGraphEdge* edge)
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{
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outEdges.push_back(edge);
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}
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inline void
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SchedGraphNode::removeInEdge(const SchedGraphEdge* edge)
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{
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assert(edge->getSink() == this);
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for (iterator I = beginInEdges(); I != endInEdges(); ++I)
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if ((*I) == edge)
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{
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inEdges.erase(I);
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break;
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}
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}
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inline void
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SchedGraphNode::removeOutEdge(const SchedGraphEdge* edge)
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{
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assert(edge->getSrc() == this);
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for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
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if ((*I) == edge)
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{
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outEdges.erase(I);
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break;
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}
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}
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//
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// class SchedGraph
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//
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/*ctor*/
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SchedGraph::SchedGraph(const BasicBlock* bb,
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const TargetMachine& target)
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{
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bbVec.push_back(bb);
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this->buildGraph(target);
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}
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/*dtor*/
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SchedGraph::~SchedGraph()
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{
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for (iterator I=begin(); I != end(); ++I)
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{
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SchedGraphNode* node = (*I).second;
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// for each node, delete its out-edges
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for (SchedGraphNode::iterator I = node->beginOutEdges();
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I != node->endOutEdges(); ++I)
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delete *I;
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// then delete the node itself.
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delete node;
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}
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}
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void
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SchedGraph::dump() const
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{
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cout << " Sched Graph for Basic Blocks: ";
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for (unsigned i=0, N=bbVec.size(); i < N; i++)
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{
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cout << (bbVec[i]->hasName()? bbVec[i]->getName() : "block")
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<< " (" << bbVec[i] << ")"
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<< ((i == N-1)? "" : ", ");
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}
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cout << endl << endl << " Actual Root nodes : ";
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for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
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cout << graphRoot->outEdges[i]->getSink()->getNodeId()
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<< ((i == N-1)? "" : ", ");
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cout << endl << " Graph Nodes:" << endl;
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for (const_iterator I=begin(); I != end(); ++I)
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cout << endl << * (*I).second;
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cout << endl;
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}
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void
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SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
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{
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// Delete and disconnect all in-edges for the node
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for (SchedGraphNode::iterator I = node->beginInEdges();
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I != node->endInEdges(); ++I)
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{
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SchedGraphNode* srcNode = (*I)->getSrc();
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srcNode->removeOutEdge(*I);
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delete *I;
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if (addDummyEdges &&
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srcNode != getRoot() &&
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srcNode->beginOutEdges() == srcNode->endOutEdges())
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{ // srcNode has no more out edges, so add an edge to dummy EXIT node
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assert(node != getLeaf() && "Adding edge that was just removed?");
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(void) new SchedGraphEdge(srcNode, getLeaf(),
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SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
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}
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}
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node->inEdges.clear();
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}
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void
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SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
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{
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// Delete and disconnect all out-edges for the node
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for (SchedGraphNode::iterator I = node->beginOutEdges();
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I != node->endOutEdges(); ++I)
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{
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SchedGraphNode* sinkNode = (*I)->getSink();
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sinkNode->removeInEdge(*I);
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delete *I;
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if (addDummyEdges &&
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sinkNode != getLeaf() &&
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sinkNode->beginInEdges() == sinkNode->endInEdges())
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{ //sinkNode has no more in edges, so add an edge from dummy ENTRY node
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assert(node != getRoot() && "Adding edge that was just removed?");
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(void) new SchedGraphEdge(getRoot(), sinkNode,
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SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
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}
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}
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node->outEdges.clear();
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}
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void
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SchedGraph::eraseIncidentEdges(SchedGraphNode* node, bool addDummyEdges)
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{
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this->eraseIncomingEdges(node, addDummyEdges);
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this->eraseOutgoingEdges(node, addDummyEdges);
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}
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void
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SchedGraph::addDummyEdges()
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{
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assert(graphRoot->outEdges.size() == 0);
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for (const_iterator I=begin(); I != end(); ++I)
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{
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SchedGraphNode* node = (*I).second;
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assert(node != graphRoot && node != graphLeaf);
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if (node->beginInEdges() == node->endInEdges())
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(void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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if (node->beginOutEdges() == node->endOutEdges())
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(void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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void
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SchedGraph::addCDEdges(const TerminatorInst* term,
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const TargetMachine& target)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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MachineCodeForVMInstr& termMvec = term->getMachineInstrVec();
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// Find the first branch instr in the sequence of machine instrs for term
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//
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unsigned first = 0;
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while (! mii.isBranch(termMvec[first]->getOpCode()))
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++first;
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assert(first < termMvec.size() &&
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"No branch instructions for BR? Ok, but weird! Delete assertion.");
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if (first == termMvec.size())
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return;
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SchedGraphNode* firstBrNode = this->getGraphNodeForInstr(termMvec[first]);
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// Add CD edges from each instruction in the sequence to the
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// *last preceding* branch instr. in the sequence
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//
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for (int i = (int) termMvec.size()-1; i > (int) first; i--)
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{
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SchedGraphNode* toNode = this->getGraphNodeForInstr(termMvec[i]);
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assert(toNode && "No node for instr generated for branch?");
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for (int j = i-1; j >= 0; j--)
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if (mii.isBranch(termMvec[j]->getOpCode()))
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{
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SchedGraphNode* brNode = this->getGraphNodeForInstr(termMvec[j]);
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assert(brNode && "No node for instr generated for branch?");
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(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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break; // only one incoming edge is enough
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}
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}
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// Add CD edges from each instruction preceding the first branch
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// to the first branch
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//
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for (int i = first-1; i >= 0; i--)
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{
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(termMvec[i]);
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assert(fromNode && "No node for instr generated for branch?");
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(void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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// Now add CD edges to the first branch instruction in the sequence
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// from all preceding instructions in the basic block.
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//
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const BasicBlock* bb = term->getParent();
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for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
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{
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if ((*II) == (const Instruction*) term) // special case, handled above
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continue;
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assert(! (*II)->isTerminator() && "Two terminators in basic block?");
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const MachineCodeForVMInstr& mvec = (*II)->getMachineInstrVec();
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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{
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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(void) new SchedGraphEdge(fromNode, firstBrNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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// If we find any other machine instructions (other than due to
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
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assert(i+d < N && "Insufficient delay slots for instruction?");
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for (unsigned j=1; j <= d; j++)
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{
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SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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}
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}
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void
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SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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const TargetMachine& target)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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for (unsigned im=0, NM=memVec.size(); im < NM; im++)
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{
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const Instruction* fromInstr = memVec[im];
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bool fromIsLoad = fromInstr->getOpcode() == Instruction::Load;
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for (unsigned jm=im+1; jm < NM; jm++)
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{
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const Instruction* toInstr = memVec[jm];
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bool toIsLoad = toInstr->getOpcode() == Instruction::Load;
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SchedGraphEdge::DataDepOrderType depOrderType;
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if (fromIsLoad)
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{
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if (toIsLoad) continue; // both instructions are loads
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depOrderType = SchedGraphEdge::AntiDep;
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}
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else
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{
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depOrderType = (toIsLoad)? SchedGraphEdge::TrueDep
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: SchedGraphEdge::OutputDep;
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}
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MachineCodeForVMInstr& fromInstrMvec=fromInstr->getMachineInstrVec();
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MachineCodeForVMInstr& toInstrMvec = toInstr->getMachineInstrVec();
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// We have two VM memory instructions, and at least one is a store.
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// Add edges between all machine load/store instructions.
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//
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for (unsigned i=0, N=fromInstrMvec.size(); i < N; i++)
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{
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MachineOpCode fromOpCode = fromInstrMvec[i]->getOpCode();
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if (mii.isLoad(fromOpCode) || mii.isStore(fromOpCode))
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{
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SchedGraphNode* fromNode =
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this->getGraphNodeForInstr(fromInstrMvec[i]);
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assert(fromNode && "No node for memory instr?");
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for (unsigned j=0, M=toInstrMvec.size(); j < M; j++)
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{
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MachineOpCode toOpCode = toInstrMvec[j]->getOpCode();
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if (mii.isLoad(toOpCode) || mii.isStore(toOpCode))
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{
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SchedGraphNode* toNode =
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this->getGraphNodeForInstr(toInstrMvec[j]);
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assert(toNode && "No node for memory instr?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::MemoryDep,
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depOrderType, 1);
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}
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}
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}
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}
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}
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}
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}
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void
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SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
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const TargetMachine& target)
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{
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assert(bbVec.size() == 1 && "Only handling a single basic block here");
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// This assumes that such hardwired registers are never allocated
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// to any LLVM value (since register allocation happens later), i.e.,
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// any uses or defs of this register have been made explicit!
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// Also assumes that two registers with different numbers are
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// not aliased!
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//
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for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
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I != regToRefVecMap.end(); ++I)
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{
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int regNum = (*I).first;
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RefVec& regRefVec = (*I).second;
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// regRefVec is ordered by control flow order in the basic block
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for (unsigned i=0; i < regRefVec.size(); ++i)
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{
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SchedGraphNode* node = regRefVec[i].first;
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unsigned int opNum = regRefVec[i].second;
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bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
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for (unsigned p=0; p < i; ++p)
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{
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SchedGraphNode* prevNode = regRefVec[p].first;
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if (prevNode != node)
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{
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unsigned int prevOpNum = regRefVec[p].second;
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bool prevIsDef =
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prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
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if (isDef)
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new SchedGraphEdge(prevNode, node, regNum,
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(prevIsDef)? SchedGraphEdge::OutputDep
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: SchedGraphEdge::AntiDep);
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else if (prevIsDef)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::TrueDep);
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}
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}
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}
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}
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}
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inline void
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CreateSSAEdge(SchedGraph* graph,
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MachineInstr* defInstr,
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SchedGraphNode* node,
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const Value* val)
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{
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// this instruction does define value `val'.
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// if there is a node for it in the same graph, add an edge.
|
|
SchedGraphNode* defNode = graph->getGraphNodeForInstr(defInstr);
|
|
if (defNode != NULL && defNode != node)
|
|
(void) new SchedGraphEdge(defNode, node, val);
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraph::addSSAEdge(SchedGraphNode* node,
|
|
const Value* val,
|
|
const TargetMachine& target)
|
|
{
|
|
if (!isa<Instruction>(val)) return;
|
|
|
|
const Instruction* thisVMInstr = node->getInstr();
|
|
const Instruction* defVMInstr = cast<const Instruction>(val);
|
|
|
|
// Phi instructions are the only ones that produce a value but don't get
|
|
// any non-dummy machine instructions. Return here as an optimization.
|
|
//
|
|
if (isa<PHINode>(defVMInstr))
|
|
return;
|
|
|
|
// Now add the graph edge for the appropriate machine instruction(s).
|
|
// Note that multiple machine instructions generated for the
|
|
// def VM instruction may modify the register for the def value.
|
|
//
|
|
MachineCodeForVMInstr& defMvec = defVMInstr->getMachineInstrVec();
|
|
const MachineInstrInfo& mii = target.getInstrInfo();
|
|
|
|
for (unsigned i=0, N=defMvec.size(); i < N; i++)
|
|
{
|
|
bool edgeAddedForInstr = false;
|
|
|
|
// First check the explicit operands
|
|
for (int o=0, N=mii.getNumOperands(defMvec[i]->getOpCode()); o < N; o++)
|
|
{
|
|
const MachineOperand& defOp = defMvec[i]->getOperand(o);
|
|
|
|
if (defOp.opIsDef()
|
|
&& (defOp.getOperandType() == MachineOperand::MO_VirtualRegister
|
|
|| defOp.getOperandType() == MachineOperand::MO_CCRegister)
|
|
&& (defOp.getVRegValue() == val))
|
|
{
|
|
CreateSSAEdge(this, defMvec[i], node, val);
|
|
edgeAddedForInstr = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Then check the implicit operands
|
|
if (! edgeAddedForInstr)
|
|
{
|
|
for (unsigned o=0, N=defMvec[i]->getNumImplicitRefs(); o < N; ++o)
|
|
if (defMvec[i]->implicitRefIsDefined(o))
|
|
{
|
|
CreateSSAEdge(this, defMvec[i], node, val);
|
|
edgeAddedForInstr = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
|
|
RegToRefVecMap& regToRefVecMap,
|
|
const TargetMachine& target)
|
|
{
|
|
SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
|
|
if (node == NULL)
|
|
return;
|
|
|
|
assert(node->getInstr() && "Should be no dummy nodes here!");
|
|
const Instruction& instr = * node->getInstr();
|
|
|
|
// Add edges for all operands of the machine instruction.
|
|
// Also, record all machine register references to add reg. deps. later.
|
|
//
|
|
for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
|
|
{
|
|
const MachineOperand& mop = minstr.getOperand(i);
|
|
|
|
// if this writes to a machine register other than the hardwired
|
|
// "zero" register, record the reference.
|
|
if (mop.getOperandType() == MachineOperand::MO_MachineRegister
|
|
&& (mop.getMachineRegNum()
|
|
!= (unsigned) target.getRegInfo().getZeroRegNum()))
|
|
{
|
|
regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node, i));
|
|
}
|
|
|
|
// ignore all other def operands
|
|
if (minstr.operandIsDefined(i))
|
|
continue;
|
|
|
|
switch(mop.getOperandType())
|
|
{
|
|
case MachineOperand::MO_VirtualRegister:
|
|
case MachineOperand::MO_CCRegister:
|
|
if (mop.getVRegValue())
|
|
addSSAEdge(node, mop.getVRegValue(), target);
|
|
break;
|
|
|
|
case MachineOperand::MO_MachineRegister:
|
|
break;
|
|
|
|
case MachineOperand::MO_SignExtendedImmed:
|
|
case MachineOperand::MO_UnextendedImmed:
|
|
case MachineOperand::MO_PCRelativeDisp:
|
|
break; // nothing to do for immediate fields
|
|
|
|
default:
|
|
assert(0 && "Unknown machine operand type in SchedGraph builder");
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Add edges for values implicitly used by the machine instruction.
|
|
// Examples include function arguments to a Call instructions or the return
|
|
// value of a Ret instruction.
|
|
//
|
|
for (unsigned i=0, N=minstr.getNumImplicitRefs(); i < N; ++i)
|
|
if (! minstr.implicitRefIsDefined(i))
|
|
addSSAEdge(node, minstr.getImplicitRef(i), target);
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
|
|
const TargetMachine& target)
|
|
{
|
|
if (isa<PHINode>(instr))
|
|
return;
|
|
|
|
MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
|
|
const MachineInstrInfo& mii = target.getInstrInfo();
|
|
RefVec refVec;
|
|
|
|
for (unsigned i=0, N=mvec.size(); i < N; i++)
|
|
for (int o=0, N = mii.getNumOperands(mvec[i]->getOpCode()); o < N; o++)
|
|
{
|
|
const MachineOperand& op = mvec[i]->getOperand(o);
|
|
|
|
if ((op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
|
op.getOperandType() == MachineOperand::MO_CCRegister)
|
|
&& op.getVRegValue() == (Value*) instr)
|
|
{
|
|
// this operand is a definition or use of value `instr'
|
|
SchedGraphNode* node = this->getGraphNodeForInstr(mvec[i]);
|
|
assert(node && "No node for machine instruction in this BB?");
|
|
refVec.push_back(make_pair(node, o));
|
|
}
|
|
}
|
|
|
|
// refVec is ordered by control flow order of the machine instructions
|
|
for (unsigned i=0; i < refVec.size(); ++i)
|
|
{
|
|
SchedGraphNode* node = refVec[i].first;
|
|
unsigned int opNum = refVec[i].second;
|
|
bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
|
|
|
|
if (isDef)
|
|
// add output and/or anti deps to this definition
|
|
for (unsigned p=0; p < i; ++p)
|
|
{
|
|
SchedGraphNode* prevNode = refVec[p].first;
|
|
if (prevNode != node)
|
|
{
|
|
bool prevIsDef = prevNode->getMachineInstr()->
|
|
operandIsDefined(refVec[p].second);
|
|
new SchedGraphEdge(prevNode, node, SchedGraphEdge::DefUseDep,
|
|
(prevIsDef)? SchedGraphEdge::OutputDep
|
|
: SchedGraphEdge::AntiDep);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
|
|
const Instruction* instr)
|
|
{
|
|
const MachineInstrInfo& mii = target.getInstrInfo();
|
|
const MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
|
|
for (unsigned i=0; i < mvec.size(); i++)
|
|
if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
|
|
{
|
|
SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
|
|
instr, mvec[i], target);
|
|
this->noteGraphNodeForInstr(mvec[i], node);
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraph::buildGraph(const TargetMachine& target)
|
|
{
|
|
const MachineInstrInfo& mii = target.getInstrInfo();
|
|
const BasicBlock* bb = bbVec[0];
|
|
|
|
assert(bbVec.size() == 1 && "Only handling a single basic block here");
|
|
|
|
// Use this data structures to note all LLVM memory instructions.
|
|
// We use this to add memory dependence edges without a second full walk.
|
|
//
|
|
vector<const Instruction*> memVec;
|
|
|
|
// Use this data structures to note any uses or definitions of
|
|
// machine registers so we can add edges for those later without
|
|
// extra passes over the nodes.
|
|
// The vector holds an ordered list of references to the machine reg,
|
|
// ordered according to control-flow order. This only works for a
|
|
// single basic block, hence the assertion. Each reference is identified
|
|
// by the pair: <node, operand-number>.
|
|
//
|
|
RegToRefVecMap regToRefVecMap;
|
|
|
|
// Make a dummy root node. We'll add edges to the real roots later.
|
|
graphRoot = new SchedGraphNode(0, NULL, NULL, target);
|
|
graphLeaf = new SchedGraphNode(1, NULL, NULL, target);
|
|
|
|
//----------------------------------------------------------------
|
|
// First add nodes for all the machine instructions in the basic block
|
|
// because this greatly simplifies identifying which edges to add.
|
|
// Do this one VM instruction at a time since the SchedGraphNode needs that.
|
|
// Also, remember the load/store instructions to add memory deps later.
|
|
//----------------------------------------------------------------
|
|
|
|
for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
|
|
{
|
|
const Instruction *instr = *II;
|
|
|
|
// Build graph nodes for this VM instruction
|
|
buildNodesforVMInstr(target, instr);
|
|
|
|
// Remember the load/store instructions to add memory deps later.
|
|
if (instr->getOpcode() == Instruction::Load ||
|
|
instr->getOpcode() == Instruction::Store)
|
|
memVec.push_back(instr);
|
|
}
|
|
|
|
//----------------------------------------------------------------
|
|
// Now add edges for the following (all are incoming edges except (4)):
|
|
// (1) operands of the machine instruction, including hidden operands
|
|
// (2) machine register dependences
|
|
// (3) memory load/store dependences
|
|
// (3) other resource dependences for the machine instruction, if any
|
|
// (4) output dependences when multiple machine instructions define the
|
|
// same value; all must have been generated from a single VM instrn
|
|
// (5) control dependences to branch instructions generated for the
|
|
// terminator instruction of the BB. Because of delay slots and
|
|
// 2-way conditional branches, multiple CD edges are needed
|
|
// (see addCDEdges for details).
|
|
// Also, note any uses or defs of machine registers.
|
|
//
|
|
//----------------------------------------------------------------
|
|
|
|
// First, add edges to the terminator instruction of the basic block.
|
|
this->addCDEdges(bb->getTerminator(), target);
|
|
|
|
// Then add memory dep edges: store->load, load->store, and store->store
|
|
this->addMemEdges(memVec, target);
|
|
|
|
// Then add other edges for all instructions in the block.
|
|
// Do this in machine code order and find all references to machine regs.
|
|
MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
|
|
for (unsigned i=0, N=mvec.size(); i < N; i++)
|
|
addEdgesForInstruction(*mvec[i], regToRefVecMap, target);
|
|
|
|
// Since the code is no longer in SSA form, add output dep. edges
|
|
// between machine instructions that define the same Value, and anti-dep.
|
|
// edges from those to other machine instructions for the same VM instr.
|
|
// We assume that all machine instructions that define a value are
|
|
// generated from the VM instruction corresponding to that value.
|
|
//
|
|
for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
|
|
{
|
|
const Instruction *instr = *II;
|
|
this->addNonSSAEdgesForValue(instr, target);
|
|
}
|
|
|
|
// Then add edges for dependences on machine registers
|
|
this->addMachineRegEdges(regToRefVecMap, target);
|
|
|
|
// Finally, add edges from the dummy root and to dummy leaf
|
|
this->addDummyEdges();
|
|
}
|
|
|
|
|
|
//
|
|
// class SchedGraphSet
|
|
//
|
|
|
|
/*ctor*/
|
|
SchedGraphSet::SchedGraphSet(const Method* _method,
|
|
const TargetMachine& target) :
|
|
method(_method)
|
|
{
|
|
buildGraphsForMethod(method, target);
|
|
}
|
|
|
|
|
|
/*dtor*/
|
|
SchedGraphSet::~SchedGraphSet()
|
|
{
|
|
// delete all the graphs
|
|
for (iterator I=begin(); I != end(); ++I)
|
|
delete (*I).second;
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraphSet::dump() const
|
|
{
|
|
cout << "======== Sched graphs for method `"
|
|
<< (method->hasName()? method->getName() : "???")
|
|
<< "' ========" << endl << endl;
|
|
|
|
for (const_iterator I=begin(); I != end(); ++I)
|
|
(*I).second->dump();
|
|
|
|
cout << endl << "====== End graphs for method `"
|
|
<< (method->hasName()? method->getName() : "")
|
|
<< "' ========" << endl << endl;
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraphSet::buildGraphsForMethod(const Method *method,
|
|
const TargetMachine& target)
|
|
{
|
|
for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI)
|
|
{
|
|
SchedGraph* graph = new SchedGraph(*BI, target);
|
|
this->noteGraphForBlock(*BI, graph);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
ostream&
|
|
operator<<(ostream& os, const SchedGraphEdge& edge)
|
|
{
|
|
os << "edge [" << edge.src->getNodeId() << "] -> ["
|
|
<< edge.sink->getNodeId() << "] : ";
|
|
|
|
switch(edge.depType) {
|
|
case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
|
|
case SchedGraphEdge::DefUseDep: os<< "Reg Value " << edge.val; break;
|
|
case SchedGraphEdge::MemoryDep: os<< "Mem Value " << edge.val; break;
|
|
case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
|
|
case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
|
|
default: assert(0); break;
|
|
}
|
|
|
|
os << " : delay = " << edge.minDelay << endl;
|
|
|
|
return os;
|
|
}
|
|
|
|
ostream&
|
|
operator<<(ostream& os, const SchedGraphNode& node)
|
|
{
|
|
printIndent(4, os);
|
|
os << "Node " << node.nodeId << " : "
|
|
<< "latency = " << node.latency << endl;
|
|
|
|
printIndent(6, os);
|
|
|
|
if (node.getMachineInstr() == NULL)
|
|
os << "(Dummy node)" << endl;
|
|
else
|
|
{
|
|
os << *node.getMachineInstr() << endl;
|
|
|
|
printIndent(6, os);
|
|
os << node.inEdges.size() << " Incoming Edges:" << endl;
|
|
for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
|
|
{
|
|
printIndent(8, os);
|
|
os << * node.inEdges[i];
|
|
}
|
|
|
|
printIndent(6, os);
|
|
os << node.outEdges.size() << " Outgoing Edges:" << endl;
|
|
for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
|
|
{
|
|
printIndent(8, os);
|
|
os << * node.outEdges[i];
|
|
}
|
|
}
|
|
|
|
return os;
|
|
}
|