Andrew Trick 47c144505b misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. ... ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8		2012-03-07 05:21:52 +00:00
..
Analysis	No functionality change. Type::isSized() can be expensive, so avoid calling it	2012-03-07 02:27:53 +00:00
Archive
AsmParser	Convert assert(0) to llvm_unreachable	2012-02-07 05:05:23 +00:00
Bitcode	BitstreamWriter: Change primary output buffer to be a SmallVector instead of an	2012-02-29 20:31:09 +00:00
CodeGen	misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.	2012-03-07 05:21:52 +00:00
DebugInfo
ExecutionEngine	Fixed the 32-bit runtime dynamic loader to allocate	2012-03-01 00:15:29 +00:00
Linker	Include cctype for isdigit. Patch by Stephen Hines.	2012-03-03 09:36:58 +00:00
MC	Make MCRegisterInfo available to the the MCInstPrinter.	2012-03-05 19:33:20 +00:00
Object	[Object]	2012-03-01 22:19:54 +00:00
Support	Added -view-background to avoid waiting for each GraphViz invocation.	2012-03-07 00:18:27 +00:00
TableGen	Switch the TableGen record's string-based DenseMap key to use the new	2012-03-05 10:36:16 +00:00
Target	ARM pre-v6 assembly parsing for umull/smull.	2012-03-07 01:09:17 +00:00
Transforms	fix typos	2012-03-05 17:39:47 +00:00
VMCore	Switch this code to use hash_combine_range rather than incremental calls	2012-03-07 03:22:32 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile