mirror of
https://github.com/c64scene-ar/llvm-6502.git
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41612a9b85
to get the subtarget and that's accessible from the MachineFunction now. This helps clear the way for smaller changes where we getting a subtarget will require passing in a MachineFunction/Function as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214988 91177308-0d34-0410-b5e6-96231b3b80d8
83 lines
3.2 KiB
TableGen
83 lines
3.2 KiB
TableGen
//===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the AMD Radeon GPUs.
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//
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//===----------------------------------------------------------------------===//
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// Inversion of CCIfInReg
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class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
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// Calling convention for SI
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def CC_SI : CallingConv<[
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CCIfInReg<CCIfType<[f32, i32] , CCAssignToReg<[
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SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
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SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
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SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21
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]>>>,
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CCIfInReg<CCIfType<[i64] , CCAssignToRegWithShadow<
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[ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14 ],
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[ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR13, SGPR15 ]
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>>>,
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CCIfNotInReg<CCIfType<[f32, i32] , CCAssignToReg<[
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VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31
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]>>>,
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CCIfByVal<CCIfType<[i64] , CCAssignToRegWithShadow<
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[ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14 ],
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[ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR13, SGPR15 ]
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>>>
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]>;
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// Calling convention for R600
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def CC_R600 : CallingConv<[
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CCIfInReg<CCIfType<[v4f32, v4i32] , CCAssignToReg<[
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T0_XYZW, T1_XYZW, T2_XYZW, T3_XYZW, T4_XYZW, T5_XYZW, T6_XYZW, T7_XYZW,
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T8_XYZW, T9_XYZW, T10_XYZW, T11_XYZW, T12_XYZW, T13_XYZW, T14_XYZW, T15_XYZW,
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T16_XYZW, T17_XYZW, T18_XYZW, T19_XYZW, T20_XYZW, T21_XYZW, T22_XYZW,
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T23_XYZW, T24_XYZW, T25_XYZW, T26_XYZW, T27_XYZW, T28_XYZW, T29_XYZW,
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T30_XYZW, T31_XYZW, T32_XYZW
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]>>>
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]>;
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// Calling convention for compute kernels
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def CC_AMDGPU_Kernel : CallingConv<[
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CCCustom<"allocateStack">
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]>;
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def CC_AMDGPU : CallingConv<[
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CCIf<"static_cast<const AMDGPUSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).getGeneration() >="
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"AMDGPUSubtarget::SOUTHERN_ISLANDS && "
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"State.getMachineFunction().getInfo<SIMachineFunctionInfo>()"
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"->getShaderType() == ShaderType::COMPUTE",
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CCDelegateTo<CC_AMDGPU_Kernel>>,
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CCIf<"static_cast<const AMDGPUSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).getGeneration() < "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS && "
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"State.getMachineFunction().getInfo<R600MachineFunctionInfo>()"
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"->getShaderType() == ShaderType::COMPUTE",
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CCDelegateTo<CC_AMDGPU_Kernel>>,
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CCIf<"static_cast<const AMDGPUSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).getGeneration() >= "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS",
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CCDelegateTo<CC_SI>>,
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CCIf<"static_cast<const AMDGPUSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).getGeneration() < "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS",
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CCDelegateTo<CC_R600>>
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]>;
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