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https://github.com/c64scene-ar/llvm-6502.git
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d7d71a1859
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133640 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.3 KiB
C++
72 lines
2.3 KiB
C++
//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// ARM back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_ARM_H
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#define TARGET_ARM_H
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#include "ARMBaseInfo.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cassert>
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namespace llvm {
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class ARMBaseTargetMachine;
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class FunctionPass;
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class JITCodeEmitter;
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class formatted_raw_ostream;
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class MCCodeEmitter;
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class MCObjectWriter;
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class TargetAsmBackend;
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class MachineInstr;
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class ARMAsmPrinter;
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class MCInst;
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MCCodeEmitter *createARMMCCodeEmitter(const Target &,
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TargetMachine &TM,
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MCContext &Ctx);
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TargetAsmBackend *createARMAsmBackend(const Target &, const std::string &);
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FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
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JITCodeEmitter &JCE);
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FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
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FunctionPass *createARMExpandPseudoPass();
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FunctionPass *createARMGlobalMergePass(const TargetLowering* tli);
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FunctionPass *createARMConstantIslandPass();
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FunctionPass *createNEONMoveFixPass();
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FunctionPass *createMLxExpansionPass();
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FunctionPass *createThumb2ITBlockPass();
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FunctionPass *createThumb2SizeReductionPass();
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extern Target TheARMTarget, TheThumbTarget;
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void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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ARMAsmPrinter &AP);
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/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
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MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
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bool Is64Bit,
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uint32_t CPUType,
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uint32_t CPUSubtype);
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} // end namespace llvm;
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#endif
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