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https://github.com/c64scene-ar/llvm-6502.git
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2a7b41ba4d
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
101 lines
3.9 KiB
C++
101 lines
3.9 KiB
C++
//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb1InstrInfo.h"
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#include "ARM.h"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/ADT/SmallVector.h"
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#include "Thumb1InstrInfo.h"
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using namespace llvm;
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Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI), RI(*this, STI) {
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}
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unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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return 0;
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}
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void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc)));
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assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
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"Thumb1 can only copy GPR registers");
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}
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void Thumb1InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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assert((RC == ARM::tGPRRegisterClass ||
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(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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isARMLowRegister(SrcReg))) && "Unknown regclass!");
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if (RC == ARM::tGPRRegisterClass ||
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(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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isARMLowRegister(SrcReg))) {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(
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MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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}
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}
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void Thumb1InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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assert((RC == ARM::tGPRRegisterClass ||
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(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
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isARMLowRegister(DestReg))) && "Unknown regclass!");
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if (RC == ARM::tGPRRegisterClass ||
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(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
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isARMLowRegister(DestReg))) {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(
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MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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}
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}
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