mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205610 91177308-0d34-0410-b5e6-96231b3b80d8
487 lines
18 KiB
C++
487 lines
18 KiB
C++
//===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb1 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb1FrameLowering.h"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
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const MachineFrameInfo *FFI = MF.getFrameInfo();
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unsigned CFSize = FFI->getMaxCallFrameSize();
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// It's not always a good idea to include the call frame as part of the
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// stack frame. ARM (especially Thumb) has small immediate offset to
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// address the stack frame. So a large call frame can cause poor codegen
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// and may even makes it impossible to scavenge a register.
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if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
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return false;
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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static void
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emitSPUpdate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const TargetInstrInfo &TII, DebugLoc dl,
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const Thumb1RegisterInfo &MRI,
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int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
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emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
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MRI, MIFlags);
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}
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void Thumb1FrameLowering::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const Thumb1InstrInfo &TII =
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*static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
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const Thumb1RegisterInfo *RegInfo =
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static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
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if (!hasReservedCallFrame(MF)) {
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// If we have alloca, convert as follows:
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// ADJCALLSTACKDOWN -> sub, sp, sp, amount
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// ADJCALLSTACKUP -> add, sp, sp, amount
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MachineInstr *Old = I;
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DebugLoc dl = Old->getDebugLoc();
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unsigned Amount = Old->getOperand(0).getImm();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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// Replace the pseudo instruction with a new instruction...
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unsigned Opc = Old->getOpcode();
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if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
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emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
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} else {
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assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
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emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
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}
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}
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}
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MBB.erase(I);
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}
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void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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const Thumb1RegisterInfo *RegInfo =
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static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
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const Thumb1InstrInfo &TII =
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*static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
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unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
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unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
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unsigned NumBytes = MFI->getStackSize();
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assert(NumBytes >= ArgRegsSaveSize &&
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"ArgRegsSaveSize is included in NumBytes");
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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unsigned FramePtr = RegInfo->getFrameRegister(MF);
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unsigned BasePtr = RegInfo->getBaseRegister();
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int CFAOffset = 0;
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// Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
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NumBytes = (NumBytes + 3) & ~3;
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MFI->setStackSize(NumBytes);
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// Determine the sizes of each callee-save spill areas and record which frame
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// belongs to which callee-save spill areas.
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unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
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int FramePtrSpillFI = 0;
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if (ArgRegsSaveSize) {
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emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
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MachineInstr::FrameSetup);
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CFAOffset -= ArgRegsSaveSize;
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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if (!AFI->hasStackFrame()) {
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if (NumBytes - ArgRegsSaveSize != 0) {
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emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
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MachineInstr::FrameSetup);
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CFAOffset -= NumBytes - ArgRegsSaveSize;
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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return;
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}
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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int FI = CSI[i].getFrameIdx();
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switch (Reg) {
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case ARM::R8:
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case ARM::R9:
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case ARM::R10:
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case ARM::R11:
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if (STI.isTargetMachO()) {
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GPRCS2Size += 4;
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break;
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}
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// fallthrough
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case ARM::R4:
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case ARM::R5:
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case ARM::R6:
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case ARM::R7:
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case ARM::LR:
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if (Reg == FramePtr)
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FramePtrSpillFI = FI;
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GPRCS1Size += 4;
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break;
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default:
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DPRCSSize += 8;
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}
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}
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if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
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++MBBI;
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if (MBBI != MBB.end())
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dl = MBBI->getDebugLoc();
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}
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// Determine starting offsets of spill areas.
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unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
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unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
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unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
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bool HasFP = hasFP(MF);
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if (HasFP)
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AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
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NumBytes);
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AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
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AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
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AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
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NumBytes = DPRCSOffset;
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int FramePtrOffsetInBlock = 0;
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unsigned adjustedGPRCS1Size = GPRCS1Size;
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if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) {
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FramePtrOffsetInBlock = NumBytes;
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adjustedGPRCS1Size += NumBytes;
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NumBytes = 0;
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}
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if (adjustedGPRCS1Size) {
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CFAOffset -= adjustedGPRCS1Size;
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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unsigned Reg = I->getReg();
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int FI = I->getFrameIdx();
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switch (Reg) {
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case ARM::R8:
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case ARM::R9:
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case ARM::R10:
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case ARM::R11:
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case ARM::R12:
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if (STI.isTargetMachO())
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break;
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// fallthough
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case ARM::R0:
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case ARM::R1:
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case ARM::R2:
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case ARM::R3:
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case ARM::R4:
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case ARM::R5:
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case ARM::R6:
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case ARM::R7:
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case ARM::LR:
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unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
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nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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break;
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}
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}
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// Adjust FP so it point to the stack slot that contains the previous FP.
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if (HasFP) {
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FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI)
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+ GPRCS1Size + ArgRegsSaveSize;
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
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.addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
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.setMIFlags(MachineInstr::FrameSetup));
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if(FramePtrOffsetInBlock) {
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CFAOffset += FramePtrOffsetInBlock;
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unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
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nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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} else {
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unsigned CFIIndex =
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MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
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nullptr, MRI->getDwarfRegNum(FramePtr, true)));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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if (NumBytes > 508)
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// If offset is > 508 then sp cannot be adjusted in a single instruction,
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// try restoring from fp instead.
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AFI->setShouldRestoreSPFromFP(true);
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}
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if (NumBytes) {
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// Insert it after all the callee-save spills.
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emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
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MachineInstr::FrameSetup);
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if (!HasFP) {
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CFAOffset -= NumBytes;
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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}
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if (STI.isTargetELF() && HasFP)
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MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
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AFI->getFramePtrSpillOffset());
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AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
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AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
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AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
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// Thumb1 does not currently support dynamic stack realignment. Report a
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// fatal error rather then silently generate bad code.
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if (RegInfo->needsStackRealignment(MF))
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report_fatal_error("Dynamic stack realignment not supported for thumb1.");
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// If we need a base pointer, set it up here. It's whatever the value
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// of the stack pointer is at this point. Any variable size objects
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// will be allocated after this, so we can still use the base pointer
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// to reference locals.
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if (RegInfo->hasBasePointer(MF))
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
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.addReg(ARM::SP));
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// If the frame has variable sized objects then the epilogue must restore
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// the sp from fp. We can assume there's an FP here since hasFP already
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// checks for hasVarSizedObjects.
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if (MFI->hasVarSizedObjects())
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AFI->setShouldRestoreSPFromFP(true);
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}
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static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
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if (MI->getOpcode() == ARM::tLDRspi &&
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MI->getOperand(1).isFI() &&
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isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
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return true;
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else if (MI->getOpcode() == ARM::tPOP) {
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// The first two operands are predicates. The last two are
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// imp-def and imp-use of SP. Check everything in between.
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for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
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if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
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return false;
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return true;
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}
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return false;
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}
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void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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assert((MBBI->getOpcode() == ARM::tBX_RET ||
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MBBI->getOpcode() == ARM::tPOP_RET) &&
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"Can only insert epilog into returning blocks");
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DebugLoc dl = MBBI->getDebugLoc();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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const Thumb1RegisterInfo *RegInfo =
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static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
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const Thumb1InstrInfo &TII =
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*static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
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unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
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unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
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int NumBytes = (int)MFI->getStackSize();
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assert((unsigned)NumBytes >= ArgRegsSaveSize &&
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"ArgRegsSaveSize is included in NumBytes");
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const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs();
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unsigned FramePtr = RegInfo->getFrameRegister(MF);
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if (!AFI->hasStackFrame()) {
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if (NumBytes - ArgRegsSaveSize != 0)
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emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
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} else {
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// Unwind MBBI to point to first LDR / VLDRD.
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if (MBBI != MBB.begin()) {
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do
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--MBBI;
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while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
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if (!isCSRestore(MBBI, CSRegs))
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++MBBI;
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}
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// Move SP to start of FP callee save spill area.
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NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
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AFI->getGPRCalleeSavedArea2Size() +
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AFI->getDPRCalleeSavedAreaSize() +
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ArgRegsSaveSize);
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if (AFI->shouldRestoreSPFromFP()) {
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NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
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// Reset SP based on frame pointer only if the stack frame extends beyond
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// frame pointer stack slot, the target is ELF and the function has FP, or
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// the target uses var sized objects.
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if (NumBytes) {
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assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
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"No scratch register to restore SP from FP!");
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emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
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TII, *RegInfo);
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
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ARM::SP)
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.addReg(ARM::R4));
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} else
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
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ARM::SP)
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.addReg(FramePtr));
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} else {
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if (MBBI->getOpcode() == ARM::tBX_RET &&
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&MBB.front() != MBBI &&
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std::prev(MBBI)->getOpcode() == ARM::tPOP) {
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MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
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if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
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emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
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} else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
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emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
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}
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}
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if (ArgRegsSaveSize) {
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// Unlike T2 and ARM mode, the T1 pop instruction cannot restore
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// to LR, and we can't pop the value directly to the PC since
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// we need to update the SP after popping the value. Therefore, we
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// pop the old LR into R3 as a temporary.
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// Get the last instruction, tBX_RET
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MBBI = MBB.getLastNonDebugInstr();
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assert (MBBI->getOpcode() == ARM::tBX_RET);
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// Epilogue for vararg functions: pop LR to R3 and branch off it.
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
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.addReg(ARM::R3, RegState::Define);
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emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
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.addReg(ARM::R3, RegState::Kill);
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AddDefaultPred(MIB);
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MIB.copyImplicitOps(&*MBBI);
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// erase the old tBX_RET instruction
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MBB.erase(MBBI);
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}
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}
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bool Thumb1FrameLowering::
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spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL;
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
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AddDefaultPred(MIB);
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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bool isKill = true;
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// Add the callee-saved register as live-in unless it's LR and
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// @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
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// then it's already added to the function and entry block live-in sets.
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if (Reg == ARM::LR) {
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MachineFunction &MF = *MBB.getParent();
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if (MF.getFrameInfo()->isReturnAddressTaken() &&
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|
MF.getRegInfo().isLiveIn(Reg))
|
|
isKill = false;
|
|
}
|
|
|
|
if (isKill)
|
|
MBB.addLiveIn(Reg);
|
|
|
|
MIB.addReg(Reg, getKillRegState(isKill));
|
|
}
|
|
MIB.setMIFlags(MachineInstr::FrameSetup);
|
|
return true;
|
|
}
|
|
|
|
bool Thumb1FrameLowering::
|
|
restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI,
|
|
const TargetRegisterInfo *TRI) const {
|
|
if (CSI.empty())
|
|
return false;
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
|
|
|
|
bool isVarArg = AFI->getArgRegsSaveSize() > 0;
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
|
|
AddDefaultPred(MIB);
|
|
|
|
bool NumRegs = false;
|
|
for (unsigned i = CSI.size(); i != 0; --i) {
|
|
unsigned Reg = CSI[i-1].getReg();
|
|
if (Reg == ARM::LR) {
|
|
// Special epilogue for vararg functions. See emitEpilogue
|
|
if (isVarArg)
|
|
continue;
|
|
Reg = ARM::PC;
|
|
(*MIB).setDesc(TII.get(ARM::tPOP_RET));
|
|
MIB.copyImplicitOps(&*MI);
|
|
MI = MBB.erase(MI);
|
|
}
|
|
MIB.addReg(Reg, getDefRegState(true));
|
|
NumRegs = true;
|
|
}
|
|
|
|
// It's illegal to emit pop instruction without operands.
|
|
if (NumRegs)
|
|
MBB.insert(MI, &*MIB);
|
|
else
|
|
MF.DeleteMachineInstr(MIB);
|
|
|
|
return true;
|
|
}
|