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behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206822 91177308-0d34-0410-b5e6-96231b3b80d8
528 lines
19 KiB
C++
528 lines
19 KiB
C++
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//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips16 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16InstrInfo.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include <cctype>
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using namespace llvm;
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#define DEBUG_TYPE "mips16-instrinfo"
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Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
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: MipsInstrInfo(tm, Mips::Bimm16),
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RI(*tm.getSubtargetImpl()) {}
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const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
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return RI;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned Mips16InstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned Mips16InstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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return 0;
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}
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void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.contains(DestReg) &&
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Mips::GPR32RegClass.contains(SrcReg))
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Opc = Mips::MoveR3216;
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else if (Mips::GPR32RegClass.contains(DestReg) &&
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Mips::CPU16RegsRegClass.contains(SrcReg))
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Opc = Mips::Move32R16;
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else if ((SrcReg == Mips::HI0) &&
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mfhi16, SrcReg = 0;
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else if ((SrcReg == Mips::LO0) &&
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mflo16, SrcReg = 0;
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assert(Opc && "Cannot copy registers");
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
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if (DestReg)
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MIB.addReg(DestReg, RegState::Define);
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if (SrcReg)
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MIB.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void Mips16InstrInfo::
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storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
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int64_t Offset) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
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Opc = Mips::SwRxSpImmX16;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
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addFrameIndex(FI).addImm(Offset)
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.addMemOperand(MMO);
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}
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void Mips16InstrInfo::
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loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, int64_t Offset) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
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Opc = Mips::LwRxSpImmX16;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
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.addMemOperand(MMO);
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}
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bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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MachineBasicBlock &MBB = *MI->getParent();
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switch(MI->getDesc().getOpcode()) {
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default:
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return false;
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case Mips::RetRA16:
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ExpandRetRA16(MBB, MI, Mips::JrcRa16);
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break;
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}
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MBB.erase(MI);
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return true;
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}
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
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case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
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case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
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case Mips::BnezRxImm16: return Mips::BeqzRxImm16;
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case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
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case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
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case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
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case Mips::Btnez16: return Mips::Bteqz16;
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case Mips::BtnezX16: return Mips::BteqzX16;
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case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
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case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
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case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
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case Mips::Bteqz16: return Mips::Btnez16;
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case Mips::BteqzX16: return Mips::BtnezX16;
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case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
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case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
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case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
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case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
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case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
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case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
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}
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assert(false && "Implement this function.");
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return 0;
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}
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static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
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const std::vector<CalleeSavedInfo> &CSI, unsigned Flags=0) {
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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// Add the callee-saved register as live-in. Do not add if the register is
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// RA and return address is taken, because it has already been added in
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// method MipsTargetLowering::LowerRETURNADDR.
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// It's killed at the spill, unless the register is RA and return address
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// is taken.
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unsigned Reg = CSI[e-i-1].getReg();
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switch (Reg) {
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case Mips::RA:
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case Mips::S0:
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case Mips::S1:
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MIB.addReg(Reg, Flags);
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break;
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case Mips::S2:
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break;
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default:
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llvm_unreachable("unexpected mips16 callee saved register");
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}
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}
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}
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// Adjust SP by FrameSize bytes. Save RA, S0, S1
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void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const BitVector Reserved = RI.getReservedRegs(MF);
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bool SaveS2 = Reserved[Mips::S2];
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MachineInstrBuilder MIB;
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unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
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MIB = BuildMI(MBB, I, DL, get(Opc));
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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addSaveRestoreRegs(MIB, CSI);
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if (SaveS2)
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MIB.addReg(Mips::S2);
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if (isUInt<11>(FrameSize))
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MIB.addImm(FrameSize);
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else {
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int Base = 2040; // should create template function like isUInt that
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// returns largest possible n bit unsigned integer
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int64_t Remainder = FrameSize - Base;
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MIB.addImm(Base);
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if (isInt<16>(-Remainder))
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BuildAddiuSpImm(MBB, I, -Remainder);
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else
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adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
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}
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}
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// Adjust SP by FrameSize bytes. Restore RA, S0, S1
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void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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MachineFunction *MF = MBB.getParent();
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MachineFrameInfo *MFI = MF->getFrameInfo();
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const BitVector Reserved = RI.getReservedRegs(*MF);
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bool SaveS2 = Reserved[Mips::S2];
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MachineInstrBuilder MIB;
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unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
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Mips::Restore16:Mips::RestoreX16;
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if (!isUInt<11>(FrameSize)) {
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unsigned Base = 2040;
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int64_t Remainder = FrameSize - Base;
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FrameSize = Base; // should create template function like isUInt that
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// returns largest possible n bit unsigned integer
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if (isInt<16>(Remainder))
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BuildAddiuSpImm(MBB, I, Remainder);
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else
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adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
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}
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MIB = BuildMI(MBB, I, DL, get(Opc));
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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addSaveRestoreRegs(MIB, CSI, RegState::Define);
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if (SaveS2)
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MIB.addReg(Mips::S2, RegState::Define);
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MIB.addImm(FrameSize);
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}
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// Adjust SP by Amount bytes where bytes can be up to 32bit number.
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// This can only be called at times that we know that there is at least one free
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// register.
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// This is clearly safe at prologue and epilogue.
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//
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void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Reg1, unsigned Reg2) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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// MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
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// unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
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// unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
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//
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// li reg1, constant
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// move reg2, sp
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// add reg1, reg1, reg2
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// move sp, reg1
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//
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//
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MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
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MIB1.addImm(Amount).addImm(-1);
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MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
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MIB2.addReg(Mips::SP, RegState::Kill);
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MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
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MIB3.addReg(Reg1);
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MIB3.addReg(Reg2, RegState::Kill);
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MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
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Mips::SP);
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MIB4.addReg(Reg1, RegState::Kill);
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}
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void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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assert(false && "adjust stack pointer amount exceeded");
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}
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/// Adjust SP by Amount bytes.
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void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
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BuildAddiuSpImm(MBB, I, Amount);
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else
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adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
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}
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/// This function generates the sequence of instructions needed to get the
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/// result of adding register REG and immediate IMM.
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unsigned
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Mips16InstrInfo::loadImmediate(unsigned FrameReg,
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int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned &NewImm) const {
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//
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// given original instruction is:
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// Instr rx, T[offset] where offset is too big.
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//
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// lo = offset & 0xFFFF
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// hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
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//
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// let T = temporary register
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// li T, hi
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// shl T, 16
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// add T, Rx, T
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//
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RegScavenger rs;
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int32_t lo = Imm & 0xFFFF;
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NewImm = lo;
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int Reg =0;
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int SpReg = 0;
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rs.enterBasicBlock(&MBB);
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rs.forward(II);
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//
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// We need to know which registers can be used, in the case where there
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// are not enough free registers. We exclude all registers that
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// are used in the instruction that we are helping.
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// // Consider all allocatable registers in the register class initially
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BitVector Candidates =
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RI.getAllocatableSet
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(*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
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// Exclude all the registers being used by the instruction.
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for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = II->getOperand(i);
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if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
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!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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Candidates.reset(MO.getReg());
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}
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//
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// If the same register was used and defined in an instruction, then
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// it will not be in the list of candidates.
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//
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// we need to analyze the instruction that we are helping.
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// we need to know if it defines register x but register x is not
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// present as an operand of the instruction. this tells
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// whether the register is live before the instruction. if it's not
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// then we don't need to save it in case there are no free registers.
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//
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int DefReg = 0;
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for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = II->getOperand(i);
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if (MO.isReg() && MO.isDef()) {
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DefReg = MO.getReg();
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break;
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}
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}
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//
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BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
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Available &= Candidates;
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//
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// we use T0 for the first register, if we need to save something away.
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// we use T1 for the second register, if we need to save something away.
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//
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unsigned FirstRegSaved =0, SecondRegSaved=0;
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unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
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Reg = Available.find_first();
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if (Reg == -1) {
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Reg = Candidates.find_first();
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Candidates.reset(Reg);
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if (DefReg != Reg) {
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FirstRegSaved = Reg;
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FirstRegSavedTo = Mips::T0;
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copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
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}
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}
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else
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Available.reset(Reg);
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BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
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NewImm = 0;
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if (FrameReg == Mips::SP) {
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SpReg = Available.find_first();
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if (SpReg == -1) {
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SpReg = Candidates.find_first();
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// Candidates.reset(SpReg); // not really needed
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if (DefReg!= SpReg) {
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SecondRegSaved = SpReg;
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SecondRegSavedTo = Mips::T1;
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}
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if (SecondRegSaved)
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copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
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}
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else
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Available.reset(SpReg);
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copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
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BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
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.addReg(Reg);
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}
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else
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BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
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.addReg(Reg, RegState::Kill);
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if (FirstRegSaved || SecondRegSaved) {
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II = std::next(II);
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if (FirstRegSaved)
|
|
copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
|
|
if (SecondRegSaved)
|
|
copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
|
|
}
|
|
return Reg;
|
|
}
|
|
|
|
unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
|
|
return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
|
|
Opc == Mips::Bimm16 ||
|
|
Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
|
|
Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
|
|
Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
|
|
Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
|
|
Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
|
|
Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
|
|
Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
|
|
Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
|
|
Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
|
|
Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
|
|
}
|
|
|
|
void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned Opc) const {
|
|
BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
|
|
}
|
|
|
|
|
|
const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
|
|
if (validSpImm8(Imm))
|
|
return get(Mips::AddiuSpImm16);
|
|
else
|
|
return get(Mips::AddiuSpImmX16);
|
|
}
|
|
|
|
void Mips16InstrInfo::BuildAddiuSpImm
|
|
(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
|
|
DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
|
|
BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
|
|
}
|
|
|
|
const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
|
|
return new Mips16InstrInfo(TM);
|
|
}
|
|
|
|
bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
|
|
int64_t Amount) {
|
|
switch (Opcode) {
|
|
case Mips::LbRxRyOffMemX16:
|
|
case Mips::LbuRxRyOffMemX16:
|
|
case Mips::LhRxRyOffMemX16:
|
|
case Mips::LhuRxRyOffMemX16:
|
|
case Mips::SbRxRyOffMemX16:
|
|
case Mips::ShRxRyOffMemX16:
|
|
case Mips::LwRxRyOffMemX16:
|
|
case Mips::SwRxRyOffMemX16:
|
|
case Mips::SwRxSpImmX16:
|
|
case Mips::LwRxSpImmX16:
|
|
return isInt<16>(Amount);
|
|
case Mips::AddiuRxRyOffMemX16:
|
|
if ((Reg == Mips::PC) || (Reg == Mips::SP))
|
|
return isInt<16>(Amount);
|
|
return isInt<15>(Amount);
|
|
}
|
|
llvm_unreachable("unexpected Opcode in validImmediate");
|
|
}
|
|
|
|
/// Measure the specified inline asm to determine an approximation of its
|
|
/// length.
|
|
/// Comments (which run till the next SeparatorString or newline) do not
|
|
/// count as an instruction.
|
|
/// Any other non-whitespace text is considered an instruction, with
|
|
/// multiple instructions separated by SeparatorString or newlines.
|
|
/// Variable-length instructions are not handled here; this function
|
|
/// may be overloaded in the target code to do that.
|
|
/// We implement the special case of the .space directive taking only an
|
|
/// integer argument, which is the size in bytes. This is used for creating
|
|
/// inline code spacing for testing purposes using inline assembly.
|
|
///
|
|
unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
|
|
const MCAsmInfo &MAI) const {
|
|
|
|
|
|
// Count the number of instructions in the asm.
|
|
bool atInsnStart = true;
|
|
unsigned Length = 0;
|
|
for (; *Str; ++Str) {
|
|
if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
|
|
strlen(MAI.getSeparatorString())) == 0)
|
|
atInsnStart = true;
|
|
if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
|
|
if (strncmp(Str, ".space", 6)==0) {
|
|
char *EStr; int Sz;
|
|
Sz = strtol(Str+6, &EStr, 10);
|
|
while (isspace(*EStr)) ++EStr;
|
|
if (*EStr=='\0') {
|
|
DEBUG(dbgs() << "parsed .space " << Sz << '\n');
|
|
return Sz;
|
|
}
|
|
}
|
|
Length += MAI.getMaxInstLength();
|
|
atInsnStart = false;
|
|
}
|
|
if (atInsnStart && strncmp(Str, MAI.getCommentString(),
|
|
strlen(MAI.getCommentString())) == 0)
|
|
atInsnStart = false;
|
|
}
|
|
|
|
return Length;
|
|
}
|