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https://github.com/c64scene-ar/llvm-6502.git
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48575f6ea7
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
55 lines
1.5 KiB
CMake
55 lines
1.5 KiB
CMake
set(LLVM_TARGET_DEFINITIONS ARM.td)
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tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(ARMGenRegisterNames.inc -gen-register-enums)
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tablegen(ARMGenRegisterInfo.inc -gen-register-desc)
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tablegen(ARMGenInstrNames.inc -gen-instr-enums)
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tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
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tablegen(ARMGenCodeEmitter.inc -gen-emitter)
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tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
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tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
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tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(ARMGenDAGISel.inc -gen-dag-isel)
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tablegen(ARMGenFastISel.inc -gen-fast-isel)
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tablegen(ARMGenCallingConv.inc -gen-callingconv)
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tablegen(ARMGenSubtarget.inc -gen-subtarget)
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tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
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tablegen(ARMGenDecoderTables.inc -gen-arm-decoder)
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add_llvm_target(ARMCodeGen
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ARMAsmBackend.cpp
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ARMAsmPrinter.cpp
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ARMBaseInstrInfo.cpp
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ARMBaseRegisterInfo.cpp
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ARMCodeEmitter.cpp
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ARMConstantIslandPass.cpp
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ARMConstantPoolValue.cpp
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ARMELFWriterInfo.cpp
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ARMExpandPseudoInsts.cpp
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ARMFastISel.cpp
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ARMFrameInfo.cpp
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ARMGlobalMerge.cpp
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ARMHazardRecognizer.cpp
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ARMISelDAGToDAG.cpp
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ARMISelLowering.cpp
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ARMInstrInfo.cpp
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ARMJITInfo.cpp
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ARMMCCodeEmitter.cpp
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ARMLoadStoreOptimizer.cpp
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ARMMCAsmInfo.cpp
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ARMMCInstLower.cpp
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ARMRegisterInfo.cpp
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ARMSelectionDAGInfo.cpp
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ARMSubtarget.cpp
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ARMTargetMachine.cpp
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ARMTargetObjectFile.cpp
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NEONMoveFix.cpp
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Thumb1InstrInfo.cpp
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Thumb1FrameInfo.cpp
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Thumb1RegisterInfo.cpp
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Thumb2ITBlockPass.cpp
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Thumb2InstrInfo.cpp
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Thumb2RegisterInfo.cpp
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Thumb2SizeReduction.cpp
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)
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