mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-17 18:31:04 +00:00
1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
2.8 KiB
LLVM
63 lines
2.8 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
|
|
; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=SI %s
|
|
; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=CI %s
|
|
|
|
@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
|
|
@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
|
|
|
|
; EG-CHECK: {{^}}local_memory_two_objects:
|
|
|
|
; Check that the LDS size emitted correctly
|
|
; EG-CHECK: .long 166120
|
|
; EG-CHECK-NEXT: .long 8
|
|
; SI-CHECK: .long 47180
|
|
; SI-CHECK-NEXT: .long 38792
|
|
|
|
; We would like to check the the lds writes are using different
|
|
; addresses, but due to variations in the scheduler, we can't do
|
|
; this consistently on evergreen GPUs.
|
|
; EG-CHECK: LDS_WRITE
|
|
; EG-CHECK: LDS_WRITE
|
|
; SI-CHECK: ds_write_b32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
|
|
; SI-CHECK-NOT: ds_write_b32 {{v[0-9]*}}, v[[ADDRW]]
|
|
|
|
; GROUP_BARRIER must be the last instruction in a clause
|
|
; EG-CHECK: GROUP_BARRIER
|
|
; EG-CHECK-NEXT: ALU clause
|
|
|
|
; Make sure the lds reads are using different addresses, at different
|
|
; constant offsets.
|
|
; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
|
|
; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
|
|
; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}}
|
|
; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]] [M0]
|
|
; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16 [M0]
|
|
; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]] [M0]
|
|
|
|
define void @local_memory_two_objects(i32 addrspace(1)* %out) {
|
|
entry:
|
|
%x.i = call i32 @llvm.r600.read.tidig.x() #0
|
|
%arrayidx = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
|
|
store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
|
|
%mul = shl nsw i32 %x.i, 1
|
|
%arrayidx1 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
|
|
store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
|
|
%sub = sub nsw i32 3, %x.i
|
|
call void @llvm.AMDGPU.barrier.local()
|
|
%arrayidx2 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
|
|
%0 = load i32 addrspace(3)* %arrayidx2, align 4
|
|
%arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %x.i
|
|
store i32 %0, i32 addrspace(1)* %arrayidx3, align 4
|
|
%arrayidx4 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
|
|
%1 = load i32 addrspace(3)* %arrayidx4, align 4
|
|
%add = add nsw i32 %x.i, 4
|
|
%arrayidx5 = getelementptr inbounds i32 addrspace(1)* %out, i32 %add
|
|
store i32 %1, i32 addrspace(1)* %arrayidx5, align 4
|
|
ret void
|
|
}
|
|
|
|
declare i32 @llvm.r600.read.tidig.x() #0
|
|
declare void @llvm.AMDGPU.barrier.local()
|
|
|
|
attributes #0 = { readnone }
|