Gerolf Hoflehner 48e1bd7287 MachineCombiner Pass for selecting faster instruction ... sequence - AArch64 target support This patch turns off madd/msub generation in the DAGCombiner and generates them in the MachineCombiner instead. It replaces the original code sequence with the combined sequence when it is beneficial to do so. When there is no machine model support it always generates the madd/msub instruction. This is true also when the objective is to optimize for code size: when the combined sequence is shorter is always chosen and does not get evaluated. When there is a machine model the combined instruction sequence is evaluated for critical path and resource length using machine trace metrics and the original code sequence is replaced when it is determined to be faster. rdar://16319955 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214669 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-03 22:03:40 +00:00
..
Analysis
Assembler	verify-uselistorder: Change the default -num-shuffles=5	2014-07-31 18:46:24 +00:00
Bindings
Bitcode	UseListOrder: Fix blockaddress use-list order	2014-08-01 22:27:19 +00:00
BugPoint
CodeGen	MachineCombiner Pass for selecting faster instruction	2014-08-03 22:03:40 +00:00
DebugInfo	Cleanup this test some more.	2014-08-01 23:01:32 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation	[ASan] Use metadata to pass source-level information from Clang to ASan.	2014-08-02 00:35:50 +00:00
Integer
JitListener
Linker
LTO
MC	tlbia support	2014-08-02 20:16:29 +00:00
Object
Other
TableGen
tools	InstrProf: Allow multiple functions with the same name	2014-08-01 22:50:07 +00:00
Transforms	[SimplifyCFG] fix accessing deleted PHINodes in switch-to-table conversion.	2014-08-02 23:41:54 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh