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This is a follow up to r227113. It is now required to use the amdgcn target for SI and newer GPUs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227316 91177308-0d34-0410-b5e6-96231b3b80d8
234 lines
5.0 KiB
C++
234 lines
5.0 KiB
C++
//=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief AMDGPU specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
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#define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
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#include "AMDGPU.h"
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#include "AMDGPUFrameLowering.h"
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPUIntrinsicInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "R600ISelLowering.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "AMDGPUGenSubtargetInfo.inc"
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namespace llvm {
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class SIMachineFunctionInfo;
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class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
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public:
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enum Generation {
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R600 = 0,
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R700,
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EVERGREEN,
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NORTHERN_ISLANDS,
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SOUTHERN_ISLANDS,
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SEA_ISLANDS,
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VOLCANIC_ISLANDS,
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};
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private:
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std::string DevName;
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bool Is64bit;
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bool DumpCode;
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bool R600ALUInst;
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bool HasVertexCache;
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short TexVTXClauseSize;
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Generation Gen;
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bool FP64;
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bool FP64Denormals;
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bool FP32Denormals;
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bool CaymanISA;
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bool FlatAddressSpace;
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bool EnableIRStructurizer;
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bool EnablePromoteAlloca;
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bool EnableIfCvt;
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bool EnableLoadStoreOpt;
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unsigned WavefrontSize;
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bool CFALUBug;
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int LocalMemorySize;
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bool EnableVGPRSpilling;
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AMDGPUFrameLowering FrameLowering;
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std::unique_ptr<AMDGPUTargetLowering> TLInfo;
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std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
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InstrItineraryData InstrItins;
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Triple TargetTriple;
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public:
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AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM);
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AMDGPUSubtarget &initializeSubtargetDependencies(StringRef TT, StringRef GPU,
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StringRef FS);
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const AMDGPUFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const AMDGPUInstrInfo *getInstrInfo() const override {
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return InstrInfo.get();
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}
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const AMDGPURegisterInfo *getRegisterInfo() const override {
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return &InstrInfo->getRegisterInfo();
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}
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AMDGPUTargetLowering *getTargetLowering() const override {
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return TLInfo.get();
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}
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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bool is64bit() const {
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return Is64bit;
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}
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bool hasVertexCache() const {
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return HasVertexCache;
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}
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short getTexVTXClauseSize() const {
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return TexVTXClauseSize;
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}
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Generation getGeneration() const {
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return Gen;
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}
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bool hasHWFP64() const {
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return FP64;
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}
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bool hasCaymanISA() const {
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return CaymanISA;
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}
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bool hasFP32Denormals() const {
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return FP32Denormals;
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}
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bool hasFP64Denormals() const {
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return FP64Denormals;
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}
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bool hasFlatAddressSpace() const {
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return FlatAddressSpace;
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}
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bool hasBFE() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBFI() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBFM() const {
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return hasBFE();
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}
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bool hasBCNT(unsigned Size) const {
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if (Size == 32)
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return (getGeneration() >= EVERGREEN);
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if (Size == 64)
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return (getGeneration() >= SOUTHERN_ISLANDS);
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return false;
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}
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bool hasMulU24() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasMulI24() const {
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return (getGeneration() >= SOUTHERN_ISLANDS ||
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hasCaymanISA());
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}
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bool hasFFBL() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasFFBH() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool IsIRStructurizerEnabled() const {
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return EnableIRStructurizer;
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}
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bool isPromoteAllocaEnabled() const {
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return EnablePromoteAlloca;
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}
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bool isIfCvtEnabled() const {
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return EnableIfCvt;
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}
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bool loadStoreOptEnabled() const {
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return EnableLoadStoreOpt;
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}
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unsigned getWavefrontSize() const {
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return WavefrontSize;
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}
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unsigned getStackEntrySize() const;
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bool hasCFAluBug() const {
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assert(getGeneration() <= NORTHERN_ISLANDS);
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return CFALUBug;
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}
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int getLocalMemorySize() const {
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return LocalMemorySize;
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}
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unsigned getAmdKernelCodeChipID() const;
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bool enableMachineScheduler() const override {
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return getGeneration() <= NORTHERN_ISLANDS;
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}
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// Helper functions to simplify if statements
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bool isTargetELF() const {
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return false;
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}
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StringRef getDeviceName() const {
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return DevName;
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}
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bool dumpCode() const {
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return DumpCode;
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}
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bool r600ALUEncoding() const {
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return R600ALUInst;
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}
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bool isAmdHsaOS() const {
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return TargetTriple.getOS() == Triple::AMDHSA;
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}
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bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
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};
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} // End namespace llvm
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#endif
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